Rate converter using a register postfix type transversal filter

ABSTRACT

(M-N) 0 data are inserted for every N data of the f SL  input data by an interpolation circuit 20 for generating f SH  rate data, while filter coefficients are sequentially generated by M coefficient generators 30A to 30D at the f SH  rate. A register postfix type transversal filter 40 effectuates up rate conversion of N:M (N&lt;M) of generating f SH  rate output data from f SL  rate input data. The transversal filter 40 includes M multipliers 41A to 41D for multiplying the f SH  rate data generated by the interpolation circuit 20 with the filter coefficients sequentially applied by the coefficient generators 30A to 30D and each (M-1) delay circuits 42A to 42C and additive units 43A to 43C for delaying product outputs of the multipliers 41A to 41D by unit time delay and summing the delayed product output together.

TECHNICAL FIELD

This invention relates to a rate converter for converting the rate ofdata for exchanging data between digital circuits operating at twodifferent clock rates, and to an imaging apparatus provided with therate converter.

BACKGROUND ART

In general, for exchanging data between two digital circuits operatingat different clock rates, a rate converter is needed for converting thedata rate.

For example, when exchanging digital video signals between a digitalvideo signal processing circuit of an imager operating at a clock rateof 18 MHz and a digital video signal processing circuit of a digitalvideo tape recorder (RVTR) operating at a clock rate of 13.5 MHzpursuant to D1 standard, a rate converter, such as a 4:3-down rateconverter for converting the rate of digital video signal outputted fromthe imager from 18 MHz to 13.5 MHz, or a 3:4-up rate converter forconverting the rate of digital video signals outputted from the DVTRfrom 13.5 MHz to 18 MHz, is needed.

The imager employing a solid-state imaging device usually has a clockrate determined by the number of pixels of the solid-state imagingdevice. For example, with an imager employing 500,000 pixel solidimaging devices, the digital video signal processing circuit operates ata clock rate of 18 MHz.

With the conventional rate converter, output data of a desired outputclock rate is obtained by upconverting input data to a clock rate equalto the least common multiple of the input clock rate and the outputclock rate and by thinning out via a filter. Thus the conventional rateconverter is in need of filtering at the output clock rate equal to theabove-mentioned least common multiple.

For example, with a 4:3-down rate converter, input data at the 18 MHzclock rate is converted by the filtering shown in FIGS. 1 and 2 intooutput data having the clock rate of 13.5 MHz.

That is, with the 4:3-down rate converter, zero data is inserted at thepositions of 18 MHz clock rate input data {X_(m) } shown at A in FIG. 1which can become sampling points for 13.5 MHz as shown at B in FIG. 1for upconverting the input data to the clock rate of a frequency equalto the least common multiple of 18 MHz and 13.5 MHz, that is 54 MHz.Thus, in the frequency domain, the frequency components repeated on thebasis of 18 MHz as shown at A in FIG. 2 are now repeated at the unit ofrepetition of 54 MHz, with the frequency characteristics remainingunchanged, as shown at B in FIG. 2.

The 54 MHz clock rate data is then passed through a filter havingcharacteristics shown at C in FIG. 1 and at C in FIG. 2. That is, sincethe output clock rate is 13.5 MHz, should there be frequency componentsof not less than 6.75 MHz (one-half of 13.5 MHz) up to 27 MHz (one-halfof 54 MHz), aliasing is produced when the clock rate is set to 13.5 MHz,and hence original frequency characteristics cannot be maintained.Consequently, the data is passed through a low-pass filter forsuppressing frequency components not less than 6.75 MHz.

The data {Y_(i) } at the clock rate of 54 MHz having frequencycomponents not less than 6.75 MHz suppressed, is obtained as data Y₁ toY₁₄, that is,

    Y.sub.1 =k.sub.2 ·X.sub.4 +k.sub.8 ·X.sub.3 +k.sub.8 ·X.sub.2 +k.sub.11 ·X.sub.1

    Y.sub.2 =k.sub.0 ·X.sub.5 +k.sub.3 ·X.sub.4 +k.sub.6 ·X.sub.3 +k.sub.9 ·X.sub.2

    Y.sub.3 =k.sub.1 ·X.sub.5 +k.sub.4 ·X.sub.4 +k.sub.7 ·X.sub.3 +k.sub.10 ·X.sub.2

    Y.sub.4 =k.sub.2 ·X.sub.5 +k.sub.5 ·X.sub.4 +k.sub.8 ·X.sub.3 +k.sub.11 ·X.sub.2

    Y.sub.5 =k.sub.0 ·X.sub.6 +k.sub.3 ·X.sub.5 +k.sub.6 ·X.sub.4 +k.sub.9 ·X.sub.3

    Y.sub.6 =k.sub.1 ·X.sub.6 +k.sub.4 ·X.sub.5 +k.sub.7 ·X.sub.4 +k.sub.10 ·X.sub.3

    Y.sub.7 =k.sub.2 ·X.sub.6 +k.sub.5 ·X.sub.5 +k.sub.8 ·X.sub.4 +k.sub.11 ·X.sub.3

    Y.sub.8 =k.sub.0 ·X.sub.7 +k.sub.3 ·X.sub.6 +k.sub.6 ·X.sub.5 +k.sub.9 ·X.sub.4

    Y.sub.9 =k.sub.1 ·X.sub.7 +k.sub.4 ·X.sub.6 +k.sub.7 ·X.sub.5 +k.sub.10 ·X.sub.4

    Y.sub.10 =k.sub.2 ·X.sub.7 +k.sub.5 ·X.sub.6 +k.sub.8 ·X.sub.5 +k.sub.11 ·X.sub.4

    Y.sub.11 =k.sub.0 ·X.sub.8 +k.sub.3 ·X.sub.7 +k.sub.6 ·X.sub.6 +k.sub.9 ·X.sub.5

    Y.sub.12 =k.sub.1 ·X.sub.8 +k.sub.4 ·X.sub.7 +k.sub.7 ·X.sub.6 +k.sub.10 ·X.sub.5

    Y.sub.13 =k.sub.2 ·X.sub.8 +k.sub.5 ·X.sub.7 +k.sub.8 ·X.sub.6 +k.sub.11 ·X.sub.5

    Y.sub.14 =k.sub.0 ·X.sub.9 +k.sub.3 ·X.sub.8 +k.sub.6 ·X.sub.7 +k.sub.9 ·X.sub.6

by filtering input data X_(m) =z^(m) ·X₁ with a transfer functionrepresented by the formula (1) ##EQU1## using a transversal filteroperating at 54 MHz, with the number of taps being 12.

From the data {Y_(i) }, with the clock rate of 54 MHz, as shown at D inFIGS. 1 and 2, every three data of i=3n, i=3n+1 or i=3n+2 is extractedat the clock rate of 13.5 MHz as shown at E in FIG. 1, whereby outputdata {Y_(n) } with the clock rate of 13.5 MHz, in which frequencycharacteristics Of the input data {X_(m) } are maintained to the maximumextent, is obtained, as shown at E in FIG. 2.

With the 3:4-up rate converter, the input data {X_(n) } with the clockrate of 13.5 MHz is converted into output data {Y_(m) } with the clockrate of 18 MHz by the filtering shown in FIGS. 3 and 4.

That is, with the 3:4-up rate converter, zero data is inserted at thepositions of 13.5 MHz clock rate input data {X_(m) } shown at A in FIG.3 which can become sampling points for 18 MHz as shown at B in FIG. 3,for upconverting the input data to the clock rate of a frequency equalto the least common multiple of 18 MHz and 13.5 MHz, that is 54 MHz.Thus, in the frequency domain, the frequency components repeated on thebasis of 13.5 MHz as shown at A in FIG. 4 are now repeated at the unitof repetition of 54 MHz, with the frequency characteristics remainingunchanged, as shown at B in FIG. 4.

The data having the clock rate of 54 MHz is then passed through a filterhaving characteristics shown at C in FIGS. 3, 4. That is, since theoutput clock rate is 18 MHz, should there be frequency components of notless than 9 (one-half of 18 MHz) up to 27 MHz (one-half of 54 MHz),aliasing is produced when the clock rate is set to 18 MHz, and henceoriginal frequency characteristics cannot be maintained. Consequently,the data is passed through a low-pass filter for suppressing frequencycomponents not less than 9 MHz.

The data {Y_(i) } at the clock rate of 54 MHz, having frequencycomponents not less than 9 MHz suppressed, is obtained as data Y₁ to Y₁₄that is,

    Y.sub.1 =k.sub.3 ·X.sub.3 +k.sub.7 ·X.sub.2 +k.sub.11 ·X.sub.1

    Y.sub.2 =k.sub.0 ·X.sub.4 +k.sub.4 ·X.sub.3 +k.sub.8 ·X.sub.2

    Y.sub.3 =k.sub.1 ·X.sub.4 +k.sub.5 ·X.sub.3 +k.sub.9 ·X.sub.2

    Y.sub.4 =k.sub.2 ·X.sub.4 +k.sub.6 ·X.sub.3 +k.sub.10 ·X.sub.2

    Y.sub.5 =k.sub.3 ·X.sub.4 +k.sub.7 ·X.sub.3 +k.sub.11 ·X.sub.2

    Y.sub.6 =k.sub.0 ·X.sub.5 +k.sub.4 ·X.sub.4 +k.sub.8 ·X.sub.3

    Y.sub.7 =k.sub.1 ·X.sub.5 +k.sub.5 ·X.sub.4 +k.sub.9 ·X.sub.3

    Y.sub.8 =k.sub.2 ·X.sub.5 +k.sub.6 ·X.sub.4 +k.sub.10 ·X.sub.3

    Y.sub.9 =k.sub.3 ·X.sub.5 +k.sub.7 ·X.sub.4 +k.sub.11 ·X.sub.3

    Y.sub.10 =k.sub.0 ·X.sub.6 +k.sub.4 ·X.sub.5 +k.sub.8 ·X.sub.4

    Y.sub.11 =k.sub.1 ·X.sub.6 +k.sub.5 ·X.sub.5 +k.sub.9 ·X.sub.4

    Y.sub.12 =k.sub.2 ·X.sub.6 +k.sub.6 ·X.sub.5 +k.sub.10 ·X.sub.4

    Y.sub.13 =k.sub.3 ·X.sub.6 +k.sub.7 ·X.sub.5 +k.sub.11 ·X.sub.4

    Y.sub.14 =k.sub.0 ·X.sub.7 +k.sub.4 ·X.sub.6 +k.sub.8 ·X.sub.5

by filtering input data X_(m) =z^(m) ·X₁ with a transfer functionrepresented by the formula (2) ##EQU2## using a transversal filteroperating at 54 MHz, with the number of taps being 12.

From the data {Y_(i) }, with the clock rate of 54 MHz, as shown at D inFIGS. 3 and 4, every four data of i=4m-2, i=4m-1 i=4m or i=4m-3 is takenout at the clock rate of 18 MHz as shown at E in FIG. 3, so that outputdata {X_(n) } with the clock rate of 18 MHz, in which frequencycharacteristics of the input data {X_(m) } are maintained to the maximumextent, is obtained, as shown at E in FIG. 4.

With a M:N (M>N), such as 5:3, down rate converter, in which rateconversion of 5:3 is executed for converting f_(SH) rate input data{X_(m) } into f_(SL) rate output data {Y_(n) }, every two "0"s areinserted between respective data of the f_(SH) rate input data {X_(m) }in order to generate 3 f_(SH) rate data {Y_(i) } which is filtered by atransversal filter operating at the 3 f_(SH) rate. Every five data issampled from the 3 f_(SH) rate data {Y_(i) } to generate data {Y_(n) }having the rate of f_(SL) (F_(SL) =3/5 f_(SH)).

That is, by inserting two "0"s as shown at B in FIG. 5 between data ofthe f_(SH) rate input data as shown at A in FIG. 5 for up-conversion tothe 3 f_(SH) rate and by subsequently passing the up-converted data by atransversal filter operating at the 3 f_(SH) rate by convolution by thecoefficients shown at C in FIG. 5, data Y₁ to Y₁₆

    Y.sub.1 =k.sub.0 ·X.sub.1 +k.sub.3 ·X.sub.2 +k.sub.6 ·X.sub.3 +k.sub.9 ·X.sub.4 +k.sub.12 ·X.sub.5

    Y.sub.2 =K.sub.2 ·X.sub.2 +k.sub.5 ·X.sub.3 +k.sub.8 ·X.sub.4 +k.sub.11 ·X.sub.5 +k.sub.14 ·X.sub.6

    Y.sub.3 =k.sub.1 ·X.sub.2 +k.sub.4 ·X.sub.3 +k.sub.7 ·X.sub.4 +k.sub.10 ·X.sub.5 +k.sub.13 ·X.sub.6

    Y.sub.4 =k.sub.0 ·X.sub.2 +k.sub.2 ·X.sub.3 +k.sub.6 ·X.sub.4 +k.sub.9 +X.sub.5 +k.sub.12 ·X.sub.6

    Y.sub.5 =k.sub.2 ·X.sub.3 +k.sub.5 ·X.sub.4 +k.sub.8 ·X.sub.5 +k.sub.11 ·X.sub.6 +k.sub.14 ·X.sub.7

    Y.sub.6 =k.sub.1 +X.sub.3 +k.sub.4 ·X.sub.4 +k.sub.7 ·X.sub.5 +k.sub.10 ·X.sub.6 +k.sub.13 ·X.sub.7

    Y.sub.7 =k.sub.0 ·X.sub.3 +k.sub.3 ·X.sub.4 +k.sub.6 ·X.sub.5 +k.sub.9 ·X.sub.6 +k.sub.12 ·X.sub.7

    Y.sub.8 =k.sub.2 ·X.sub.4 +k.sub.5 ·X.sub.5 +k.sub.8 ·X.sub.6 +k.sub.11 ·X.sub.7 +k.sub.14 ·X.sub.8

    Y.sub.9 =k.sub.1 ·X.sub.4 +k.sub.4 ·X.sub.5 +k.sub.7 ·X.sub.6 +K.sub.10 ·X.sub.7 +k.sub.13 ·X.sub.8

    Y.sub.10 =k.sub.0 ·X.sub.4 +k.sub.3 ·X.sub.5 +k.sub.6 ·X.sub.6 +k.sub.9 ·X.sub.7 +k.sub.12 ·X.sub.8

    Y.sub.11 =k.sub.2 ·X.sub.5 +k.sub.5 ·X.sub.6 +k.sub.8 ·X.sub.7 +k.sub.11 ·X.sub.8 +k.sub.14 ·X.sub.9

    Y.sub.12 =k.sub.1 ·X.sub.5 +k.sub.4 ·X.sub.6 +k.sub.7 ·X.sub.7 +k.sub.10 ·X.sub.8 +k.sub.13 ·X.sub.9

    Y.sub.13 =k.sub.0 ·X.sub.5 +k.sub.3 ·X.sub.6 +k.sub.5 ·X.sub.7 +k.sub.9 ·X.sub.8 +k.sub.12 ·X.sub.9

    Y.sub.14 =k.sub.2 ·X.sub.6 +k.sub.5 ·X.sub.7 +k.sub.8 ·X.sub.8 +k.sub.11 ·X.sub.9 +k.sub.14 ·X.sub.10

    Y.sub.15 =k.sub.1 ·X.sub.6 +k.sub.4 ·X.sub.7 +k.sub.7 ·X.sub.8 +k.sub.10 ·X.sub.9 +k.sub.13 ·X.sub.10

    Y.sub.16 =k.sub.0 ·X.sub.6 +k.sub.3 ·X.sub.7 +k.sub.6 ·X.sub.8 +k.sub.9 ·X.sub.9 +k.sub.12 ·X.sub.10

are generated.

From the data {Y_(i) }, with the rate of 3 f_(SH), as shown at D in FIG.5, every five data of i=5n-4, i=5n-3 i=5n-2, i=5n-1 or i=5n, output data{Y_(n) } having the rate of f_(SL), is obtained, as shown at E in FIG.5.

With a M:N (M<N), such as 3:5, up rate converter, in which rateconversion of 3:5 is executed for converting f_(SL) rate input data{X_(m) } into f_(SH) rate output data {Y_(n)), every four "0"s areinserted between the f_(SL) rate input data {X_(m) } in order togenerate 5 f_(SL) rate data {Y_(5n) } which is filtered by a transversalfilter operating at the 5 f_(SL) rate. Every three data is sampled fromthe 5 f_(SL) rate data {Y_(5n) } to generate data {Y_(m) } having therate of f_(SH) (F_(SH) =5/3 f_(SL)).

That is, by inserting four "0"s as shown at B in FIG. 6 between data ofthe f_(SL) rate input data as shown at A in FIG. 6 for up-conversion tothe 5 f_(SL) rate and by subsequently passing the up-converted data by atransversal filter operating at the 5 f_(SL) rate by convolution by thecoefficients shown at C in FIG. 6, data Y₁ to Y₁₉

    Y.sub.1=k.sub.0·X.sub.1 +k.sub.5 ·X.sub.2 +k.sub.10 ·X.sub.3

    Y.sub.2=k.sub.4·X.sub.2 +k.sub.9 ·X.sub.3 +k.sub.14 ·X.sub.4

    Y.sub.3=k.sub.3·X.sub.2 +k.sub.8 ·X.sub.3 +k.sub.13 ·X.sub.4

    Y.sub.4=k.sub.2·X.sub.2 +k.sub.7 ·X.sub.3 +k.sub.12 ·X.sub.4

    Y.sub.5=k.sub.1·X.sub.2 +k.sub.6 ·X.sub.3 +k.sub.11 ·X.sub.4

    Y.sub.6=k.sub.0·X.sub.2 +k.sub.5 ·X.sub.3 +k.sub.10 ·X.sub.4

    Y.sub.7=k.sub.4·X.sub.3 +k.sub.9 ·X.sub.4 +k.sub.14 ·X.sub.5

    Y.sub.8=k.sub.3·X.sub.3 +k.sub.8 ·X.sub.4 +k.sub.13 ·X.sub.5

    Y.sub.9=k.sub.2·X.sub.2 +k.sub.7 ·X.sub.4 +k.sub.12 ·X.sub.5

    Y.sub.10=k.sub.1·X.sub.3 +k.sub.6 ·X.sub.4 +k.sub.11 ·X.sub.5

    Y.sub.11=k.sub.0·X.sub.3 +k.sub.5 ·X.sub.4 +k.sub.10 ·X.sub.5

    Y.sub.12=k.sub.4·X.sub.4 +k.sub.9 ·X.sub.5 +k.sub.14 ·X.sub.6

    Y.sub.13=k.sub.3·X.sub.4 +k.sub.8 ·X.sub.5 +k.sub.13 ·X.sub.6

    Y.sub.14=k.sub.2·X.sub.4 +k.sub.7 ·X.sub.5 +k.sub.12 ·X.sub.6

    Y.sub.15=k.sub.1·X.sub.4 +k.sub.6 ·X.sub.5 +k.sub.11 ·X.sub.6

    Y.sub.16=k.sub.0·X.sub.4 +k.sub.5 ·X.sub.5 +k.sub.10 ·X.sub.6

    Y.sub.17=k.sub.4·X.sub.5 +k.sub.9 ·X.sub.6 +k.sub.14 ·X.sub.7

    Y.sub.18=k.sub.3·X.sub.5 +k.sub.8 ·X.sub.6 +k.sub.13 ·X.sub.7

    Y.sub.19=k.sub.2·X.sub.5 +k.sub.7 ·X.sub.6 +k.sub.12 ·X.sub.7

are generated.

From the data {Y_(i) }, with the rate of 5 f_(S1), as shown at D in FIG.6, every three data of i=3n=2, i=3n-13 or i=3n is extracted, wherebyoutput data {Y_(m) } having the rate of f_(SH), is obtained, as shown atE in FIG. 6.

With the camera built-in type DVTR having an imager operating at a clockrate of 18 MHz and a DVTR pursuant to the D1 standard operating at theclock rate of 13.5 MHz, integrated thereto, or a so-called digitalcamcorder, it is necessary to have both the above-mentioned down rateconverter and the up rate converter, resulting in a large-sized circuitarrangement because of these rate converters.

On the other hand, with the conventional rate converter, it is necessaryto have a fast arithmetic-logical unit for executing filtering at aclock rate equal to the least common multiple of the input and outputclock rates.

With the 4:3 down rate converter for converting the 18 MHz clock rateinput data {X_(m) } into 13.5 MHz clock rate output data {Y_(n) }, thedata {Y_(i) } having the clock rate of 54 MHz, which is the least commonmultiple of the 13.5 MHz input clock rate and the 18 MHz output clockrate, obtained by the filtering by the transfer function F₁ (z) shown bythe formula (1), can be classed into the following three groups,depending on coefficients:

The first group is made up of i=3n-1 data (Y.sub.(3n-1) } havingcoefficients {k₀, k₃, k₆, k₉ }, such that

    Y.sub.2 =k.sub.0 ·X.sub.5 +k.sub.3 ·X.sub.4 +k.sub.6 ·X.sub.3 +k.sub.9 ·X.sub.2

    Y.sub.5 =k.sub.0 ·X.sub.6 +k.sub.3 ·X.sub.5 +k.sub.6 ·X.sub.4 +k.sub.9 ·X.sub.3

    Y.sub.8 =k.sub.0 ·X.sub.7 +k.sub.3 ·X.sub.6 +k.sub.6 ·X.sub.5 +k.sub.9 ·X.sub.4

    Y.sub.11 =k.sub.0 ·X.sub.8 +k.sub.3 ·X.sub.7 +k.sub.6 ·X.sub.6 +k.sub.9 ·X.sub.5

    Y.sub.14 =k.sub.0 ·X.sub.9 +k.sub.3 ·X.sub.8 +k.sub.6 ·X.sub.7 +k.sub.9 ·X.sub.6

The second group is made up of i=3n data {Y.sub.(3n) } havingcoefficients {k₁, k₄, k₇, k₁₀ }, such that

    Y.sub.3 =k.sub.1 ·X.sub.5 +k.sub.4 ·X.sub.4 +k.sub.7 ·X.sub.3 +k.sub.10 ·X.sub.2

    Y.sub.6 =k.sub.1 ·X.sub.6 +k.sub.4 ·X.sub.5 +k.sub.7 ·X.sub.4 +k.sub.10 ·X.sub.3

    Y.sub.9 =k.sub.1 ·X.sub.7 +k.sub.4 ·X.sub.6 +k.sub.7 ·X.sub.5 +k.sub.10 ·X.sub.4

    Y.sub.12 =k.sub.1 ·X.sub.8 +k.sub.4 ·X.sub.7 +k.sub.7 ·X.sub.6 +k.sub.10 ·X.sub.5

The third group is made up of i=3n=2 data {Y.sub.(3n-2) } havingcoefficients {k₂, k₅, k₈, k₁₁ }, such that

    Y.sub.1 =k.sub.2 ·X.sub.4 +k.sub.5 ·X.sub.3 +k.sub.8 ·X.sub.2 +k.sub.11 ·X.sub.1

    Y.sub.4 =k.sub.2 ·X.sub.5 +k.sub.5 ·X.sub.4 +k.sub.8 ·X.sub.3 +k.sub.11 ·X.sub.2

    Y.sub.7 =k.sub.2 ·X.sub.6 +k.sub.5 ·X.sub.5 +k.sub.8 ·X.sub.4 +k.sub.11 ·X.sub.3

    Y.sub.10 =k.sub.2 ·X.sub.7 +k.sub.5 ·X.sub.6 +k.sub.8 ·X.sub.5 +k.sub.11 ·X.sub.4

    Y.sub.13 =k.sub.2 ·X.sub.8 +k.sub.5 ·X.sub.7 +k.sub.8 ·X.sub.6 +k.sub.11 ·X.sub.5

The data {Y.sub.(3n-1) } having the group of coefficients {k₀, k₃, k₅,k₉ } may be obtained using a transversal filter of the transfer functionFa(z), that is

    Fa(z)=k.sub.0 +k.sub.3 ·z.sup.-1 +k.sub.6 ·z.sup.-2 +k.sub.9 ·z.sup.-3

The data {Y.sub.(3n) } having the group of coefficients {k₁, k₄, k₇, k₁₀} may be obtained using a transversal filter of the transfer functionFb(z), that is

    Fb(z)=k.sub.1 +k.sub.4 ·z.sup.-1 +k.sub.7 ·z.sup.-2 +k.sub.10 ·z.sup.-3

In addition, the data {Y.sub.(3n-2) } having the group of coefficients{k₂, k₅, k₈, k₁₁ } may be obtained using a transversal filter of thetransfer function Fc(z), that is

    Fc(z)=k.sub.2 +k.sub.5 ·z.sup.-1 +k.sub.8 ·z.sup.-2 +k.sub.11 ·z.sup.-3

Consequently, with the 4:3 down rate converter, the output data {Y_(n) }may be calculated by parallel operation of three transversal filtersperforming the filtering with the transfer functions Fa(z), Fb(z) andFc(z) at the input clock rate of 18 MHz, in place of upconverting theinput data of 18 MHz clock rate {X_(m) } to the clock rate of 54 MHz(the least common multiple) by inserting zero data.

Similarly, with the up rate converter of converting the input data withthe 13.5 MHz clock rate {X_(n) } into output data {Y_(m) } with the 18MHz clock rate, the data {Y_(i) } with the clock rate of 54 MHz,corresponding to the least common multiple of the 18 MHz output clockrate and the 13.5 MHz clock rate resulting from filtering by thetransfer function F₂ (z) shown by the formula (2), may be classed intofour groups, namely i=4m-2 data {Y.sub.(4m-2) } having a first group ofcoefficients {k₀, k₄, k₈ }, i=4m-1 data {Y.sub.(4m-1) } having a secondgroup of coefficients {k₁, k₅, k₉ }, l/ i=4m data {Y.sub.(4m) } having athird group of coefficients {k₂, k₆, k₁₀ } and i=4m-3 data {Y.sub.(4m-3)} having a fourth group of coefficients {k₃, k₇, k₁₁ }. Thus the outputdata {Y_(m) } may be calculated by parallel operation of fourtransversal filters performing the filtering with the transfer functions

    Fa(z)=k.sub.0 +k.sub.4 ·z.sup.-1 +k.sub.8 ·z.sup.-2

    Fb(z)=k.sub.1 +k.sub.5 ·z.sup.-1 +k.sub.9 ·z.sup.-2

    Fc(z)=k.sub.2 +k.sub.6 ·z.sup.-1 +k.sub.10 ·z.sup.-2

    Fd(z)=k.sub.3 +k.sub.7 ·z.sup.-1 +k.sub.11 ·z.sup.-2

at the input clock rate of 13.5 MHz, in place of upconverting the inputdata of 13.5 MHz clock rate {X_(n) } to the clock rate of 54 MHz (theleast common multiple) by inserting zero data.

By such parallel operation of the plural transversal filters at an inputclock rate, the necessity of providing a fast transversal filteroperated at the clock rate equal to the least common multiple of theinput and output clock rates is eliminated. However, plural transversalfilters become necessary.

Up to now, a register pre-fix type transversal filter and a registerpost-fix type transversal filter have been known.

With the register pre-fix type transversal filter, as shown in FIG. 7, atime difference of a unit time {z⁻ } corresponding to one clock isapplied to the input data {X_(n) } by delay circuits 1A, 2A and 1C. Thedelayed data is then multiplied by the filter coefficients {k₁, k₂, k₃and k₄ } by multipliers 2A, 2B, 2C and 2D, and the resulting productsare summed by an additive unit 3 to generate output data Y such that

    Y=k.sub.1 ·X.sub.4 +k.sub.2 (z.sup.-1 ·X.sub.3)+k.sub.3 (z.sup.-2 ·X.sub.2)+k.sub.4 (z.sup.-3 ·X.sub.1)

For a rate converter, a register-prefix type transversal filter has beenin use. However, such register-prefix type transversal filter is in needof a multi-input additive unit as the additive unit S. In addition, ahold time need be provided for the shift register. Thus theregister-prefix type filter is unfit for fast operation.

On the other hand, with the register-postfix type transversal filter, asshown in FIG. 8, the input data {X_(n) } is multiplied with filtercoefficients {k₁, k₂, k₃ and k₄ }, by multipliers 4A, 4B, 4C and 4D, anda time difference of a unit time {z⁻¹ } is applied to the resultingproducts. The delayed products are then summed by additive units 6A, 6Band 6C to generate output data Y such that

    Y=k.sub.1 ·X.sub.4 +(k.sub.2 ·X.sub.3)z.sup.-1 +(k.sub.3 ·X.sub.2)z.sup.-2 +(k.sub.4 ·X.sub.1)z.sup.-3

With the register post-fix type transversal filter, the delay circuitconstituting a shift register is simultaneously used as a pipelineregister. Besides, since the additive units are connected between thedelay circuits, there is no necessity of providing the hold time. Thusit is of an efficient circuit configuration for fast operation with theaid of a fast process. However, since zero is inserted in the input datain the up rate conversion, a data hold operation becomes necessaryduring filtering. However, such data holding operation cannot beperformed with the register postfix type transversal filter becausethere is no register ahead of each multiplier.

It is therefore an object of the present invention to provide the rateconverter and the imager constructed in the following manner.

Thus it is an object of the present invention to provide a rateconverter in which rate conversion may be achieved by a sole transversalfilter without necessitating a fast transversal filter operated at aclock rate equal to the least common multiple of the input and outputclock rates.

It is another object of the present invention to provide a bidirectionalrate converter having the functions of both the down rate converter andthe up rate converter.

It is another object of the present invention to provide a bidirectionalrate converter in which the circuit scale is diminished by using acommon filtering means for the down rate converter and the up rateconverter.

It is also an object of the present invention to provide an imager whichmay be reduced in size.

DISCLOSURE OF THE INVENTION

As discussed above, the principle of the rate converter resides in that,by up converting input data to a clock rate equal to the least commonmultiple of the input clock rate and the output clock rate and thinningthe up converted data by a filter, output data of desired output clockrate can be produced. Since there is no necessity of calculating dataother than the output data of the desired clock rate, rate conversionmay be achieved by a sole transversal filter operating at the outputclock rate without requiring a fast transversal filter operating at theclock rate equal to the least common multiple of the input and outputclock rates, if the filtering is performed at the output clock rate forproducing the output clock rate output data.

For example, in a 4:3 down rate converter for converting 18 MHz clockrate input data {X_(m) } into 13.5 MHz clock rate {Y_(n) } output data,output data are the data taken out at the clock rate of 13.5 MHz, thatis {Y.sub.(4m) }, {Y.sub.(4m+1) }, {Y.sub.(4m+2) } or {Y.sub.(4m+3) },from the data {Y_(i) } having the clock rate of 54 MHz equal to theleast common multiple of the input and output clock rates, produced byup converting the 10 MHz clock rate input data. For example, if{Y.sub.(4n) } is the output data, such that

    Y.sub.0 =k.sub.1 ·X.sub.4 +k.sub.4 ·X.sub.3 +k.sub.7 ·X.sub.2 +k.sub.10 ·X.sub.1

    Y.sub.4 =k.sub.2 ·X.sub.5 +k.sub.5 ·X.sub.4 +k.sub.8 ·X.sub.3 +k.sub.11 ·X.sub.2

    Y.sub.8 =k.sub.0 ·X.sub.7 +k.sub.3 ·X.sub.6 +k.sub.6 ·X.sub.5 +k.sub.9 ·X.sub.4

    Y.sub.12 =k.sub.1 ·X.sub.8 +k.sub.4 ·X.sub.7 +k.sub.7 ·X.sub.6 +k.sub.10 ·X.sub.5

    Y.sub.16 =k.sub.2 ·X.sub.9 +k.sub.5 ·X.sub.8 +k.sub.8 ·X.sub.7 +k.sub.11 ·X.sub.6

    Y.sub.20 =k.sub.0 ·X.sub.11 +k.sub.3 ·X.sub.10 +k.sub.6 ·X.sub.9 +k.sub.9 ·X.sub.8

it suffices to sequentially select outputs of three transversal filtersperforming the filtering of the transfer functions Fa(z), Fb(z) andFc(z) with the above-mentioned first to third sets of coefficients. Thatis, the output data {Y_(n) } can be produced by operating a soletransversal filter, with the first to third coefficients beingsequentially switched at the output clock rate of 13.5 MHz, with theinput data {X_(m) } being latched at the input clock rate of 18 MHz.

Similarly, in a 3:4 up rate converter for converting 13.5 MHz clock rateinput data {X_(n) } into 18 MHz clock rate {Y_(m) } output data, outputdata are data taken out at the clock rate of 18 MHz, that is {Y.sub.(3n)}, {Y.sub.(3n+1) }, {Y.sub.(3n+2) }, {Y.sub.(3n+3) }, so that, if{Y.sub.(3n+1) } is the output data,

    Y.sub.1 =k.sub.3 ·X.sub.3 +k.sub.7 ·X.sub.2 +k.sub.11 ·X.sub.1

    Y.sub.4 =k.sub.2 ·X.sub.4 +k.sub.6 ·X.sub.3 +k.sub.10 ·X.sub.2

    Y.sub.7 =k.sub.1 ·X.sub.5 +k.sub.5 ·X.sub.4 +k.sub.9 ·X.sub.3

    Y.sub.10 =k.sub.0 ·X.sub.6 +k.sub.4 ·X.sub.5 +k.sub.8 ·X.sub.4

    Y.sub.13 =k.sub.3 ·X.sub.6 +k.sub.7 ·X.sub.5 +k.sub.11 ·X.sub.4

    Y.sub.16 =k.sub.2 ·X.sub.7 +k.sub.6 ·X.sub.6 +k.sub.10 ·X.sub.5

    Y.sub.19 =k.sub.1 ·X.sub.8 +k.sub.5 ·X.sub.7 +k.sub.9 ·X.sub.6

    Y.sub.22 =k.sub.0 ·X.sub.9 +k.sub.4 ·X.sub.8 +k.sub.8 ·X.sub.7

    Y.sub.25 =k.sub.3 ·X.sub.9 +k.sub.7 ·X.sub.8 +k.sub.11 ·X.sub.7

    Y.sub.28 =k.sub.2 ·X.sub.10 +k.sub.6 ·X.sub.9 +k.sub.10 ·X.sub.8

so that it suffices to sequentially select outputs of four transversalfilters performing the filtering of the transfer functions Fa(z), Fb(z),Fc(z) and Fd(z) with the above-mentioned first to fourth sets ofcoefficients. That is, the output data {Y_(m) } can be obtained byoperating a sole transversal filter, with the first to fourthcoefficients being sequentially switched at the output clock rate of 18MHz, with the input data {X_(n) } being latched at the input clock rateof 13.5 MHz.

Thus, in accordance with the present invention, f_(SH) rate data aregenerated by inserting M-N 0 data for every N data of f_(SL) data inputdata by interpolation, and the f_(SH) rate data is filtered by aregister postfix type transversal filter having M multiplierssequentially fed with filter coefficients at the f_(SH) rate from Mcoefficient generators, in order to perform up rate conversion of N:M(N<M). It is possible with the present rate converter to achieve N:N+1up rate conversion by setting so that M-N=1. It is also possible withthe present rate converter to achieve N:N+2 up rate conversion bysetting so that M-N=2. Consequently, with the present rate converter, uprate conversion of N:M (N<M) may be achieved by a register postfix typetransversal filter without requiring a fast transversal filter operatingat a clock rate equal to the least common multiple of the input andoutput clock rates, whereby f_(SH) output data may be generated fromf_(SL) input data.

Also, with the present invention, f_(SH) rate input data is filtered bya register postfix type transversal filter having M multiplierssequentially fed with filter coefficients at a f_(SH) rate, and outputdata of the transversal filter is thinned by a thinning circuit in orderto effect down rate conversion of M:N (M>N) for producing f_(SL) outputdata from the f_(SH) rate input data. It is possible with the presentrate converter to achieve N+1: N down rate conversion by setting so thatM=N+1. It is also possible with the present rate converter to achieveN+2:N down rate conversion by setting so that M=N+2. Consequently, withthe present rate converter, down rate conversion of N:M (M>N) may beachieved by a register postfix type transversal filter without requiringa fast transversal filter operating at a clock rate equal to the leastcommon multiple of the input and output clock rates, whereby f_(SL)output data may be generated from f_(SH) input data.

Also, according to the present invention, the connection of theinterpolation circuit for inserting M-N 0 data for every N data forgenerating f_(SH) rate data from the f_(SL) rate input data and thethinning circuit for thinning the f_(SH) rate filter output of thetransversal filter to the register postfix type transversal filter forfiltering f_(SH) rate data based upon filter coefficients sequentiallyapplied at f_(SH) rate from M coefficient generators is changed over byan input changeover circuit and an output changeover circuit in order toexecute up rate conversion by N:M, where N<M, of generating f_(SH) rateoutput data from the f_(SL) rate input data and down rate conversion byM:N, where M>N, of generating f_(SL) rate output data from the f_(SH)rate input data. It is possible with the present rate converter toeffectuate up rate conversion of N:N+1, where M=N+1, and down rateconversion of N+1: N, where M=N+1. It is also possible with the presentrate converter to effectuate down rate conversion of N+2:N, where M=N+2.Consequently, with the present rate converter, bidirectional rateconversion of up rate conversion of N:M (N<M) of generating f_(SH) rateoutput data from f_(SL) rate input data and down rate conversion of M:N(M>N) of generating f_(SL) rate output data from f_(SH) rate input datamay be achieved by a register postfix type transversal filter withoutrequiring a fast transversal filter operating at a clock rate equal tothe least common multiple of the input and output clock rates. Thus,with the present invention, filtering means may be used in common by thedown rate converter and the up rate converter for providing abidirectional rate converter having a reduced circuit scale.

With an imager according to the present invention, f_(SL) rate seconddigital video signals are generated from f_(SH) rate first digitalsignals produced by the imaging means during the recording mode by thebidirectional rate converter according to the present invention. Duringthe reproducing mode, f_(SH) rate first digital video signals aregenerated from f_(SL) rate second digital video signals obtained by therecording/reproducing means by up rate conversion of m:N where M>N. Thisenables the imager to be reduced in size.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the operating principle of a conventional 4:3 down rateconverter on the time axis.

FIG. 2 shows the operating principle of the above 4:3 down rateconverter on the frequency axis.

FIG. 3 shows the operating principle of a conventional 3:4 up rateconverter on the time axis.

FIG. 4 shows the operating principle of a conventional 3:4 up rateconverter on the frequency axis.

FIG. 5 shows the operating principle of a conventional 5:3 down rateconverter on the time axis.

FIG. 6 shows the operating principle of a conventional 3:5 up rateconverter on the time axis.

FIG. 7 is a block diagram showing an arrangement of a register prefixtype transversal filter.

FIG. 8 is a block diagram showing an arrangement of a register postfixtype transversal filter.

FIG. 9 is a block diagram showing an arrangement of a 3:4 up rateconverter according to the present invention.

FIG. 10 is a block diagram showing a practical arrangement of aninterpolating circuit in the above 3:4 up rate converter.

FIG. 11 is a timing chart showing the operation of the aboveinterpolating circuit.

FIG. 12 shows the contents of the arithmetic-logical operations in theabove 3:4 up rate converter.

FIG. 13 is a block diagram showing an arrangement of the 3:4 down rateconverter according to the present invention.

FIG. 14 is a block diagram showing an arrangement of a 3:4 down rateconverter according to the present invention.

FIG. 15 is a conceptual block diagram showing an arrangement of theabove bidirectional rate converter,

FIG. 16 is a block diagram showing a practical arrangement of a rateconversion block in the above bidirectional rate converter.

FIG. 17 is a timing chart for illustrating the interpolation executed bythe rate conversion block.

FIG. 18 is a timing chart for illustrating the thinning executed by therate conversion block.

FIG. 19 is a block diagram showing a practical arrangement of a digitalfilter block in the above bidirectional rate converter.

FIG. 20 is a block diagram showing an arrangement of a 5:3 down rateconverter according to the present invention.

FIG. 21 is a block diagram showing an arrangement of a 3:5 up rateconverter according to the present invention.

FIG. 22 is a block diagram showing an arrangement of a bidirectionalrate converter according to the present invention.

FIG. 23 is a block diagram showing a practical arrangement of a rateconversion block in the above bidirectional rate converter.

FIG. 24 is a block diagram showing a practical arrangement of a digitalfilter block in the above bidirectional rate converter.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to the drawings, a preferred embodiment of the presentinvention will be explained in detail.

The rate converter according to the present invention is configured asshown for example in the block diagram of FIG. 9.

In the first embodiment, shown in FIG. 9, the present invention isapplied to an up converter for executing 3:4 up rate conversion ofconverting input data {X_(n) } having a rate of f_(SL) (f_(SL) =13.5MHz) into output data {Y_(m) } having a rate of f_(SH) (f_(SH) =18 MHz).The up rate converter comprises an interpolation circuit 20 forgenerating f_(SH) rate by interpolation on input data {X_(n) } of thef_(SL) entered via an input terminal 10, four coefficient generators30A, 30B, 30C and 30D for sequentially outputting filter coefficientsand a transversal filter 40 for filtering f_(SH) rate data generated bythe interpolating circuit 20 based on the filter coefficients foroutputting f_(SH) rate output data {Y_(m) } at an output terminal 50.

The interpolating circuit 20 generates f_(SH) rate data by inserting one0 data for every three data of the f_(SL) rate input data {X_(n) }supplied via the input terminal 10, and is configured as shown forexample in the block diagram of FIG. 10.

The interpolating circuit 20 includes a divide-by-4 counter 22, forcounting 18 MHz clocks CK(f_(SH)) supplied thereto via the clock inputterminal 21 and an OR gate 23 fed with a carry output of the divide-by-4counter 22 and the above-mentioned clock CK(f_(SH)). The interpolationcircuit also includes a first D-flipflop 24 the data terminal of whichis fed with input data {X_(n) } of the f_(SL) rate synchronized with the13.5 MHz clock CK(f_(SL)) via the input terminal 10, an AND gate 28 fedwith a latch output by the first D-flipflop 24 and with a carry Co fromthe divide-by-4 counter 22 via an inverter 25, and the second D-flipflop27 the data input terminal of which is fed with a gate output data ofthe AND gate 26.

The divide-by-4 counter 22 outputs a carry Co at an interval of fourclocks by counting 18 MHz clocks CK(f_(SH)) fed via the clock inputterminal 21. The OR gate 23 ANDs the clock CK(f_(SH)) and the carry Cooutputted from the divide-by-4 counter 22 in order to generate clocksd-CK having clock interruption at a rate of one of four clocks, as shownin FIG. 11.

The first D-flipflop 24 has its clock input terminal fed with the clockd-CK generated by the OR gate 23, and latches by the clock d-CK thef_(SL) rate input data {X_(n) } synchronized with the 13.5 MHz clocksCK(f_(SH)) supplied via the input terminal 10.

The AND circuit 28 ANDs the latched output data of the first D-flipflop24 and the carry Co outputted by the divide-by-4 counter 22 and invertedby an inverter 25 in order to convert the inverted data by the inverter25 into 0 data which is inserted into latch output data of the firstD-flipflop 24.

The second D-flipflop 27 latches the output data of the AND gate 26 bythe 18 MHz clocks CK(f_(SH)) for generating f_(SH) rate data in which 0data is inserted at every three data of the f_(SL) rate input data{X_(n) } synchronized with the 13.5 MHz clocks CK(f_(SL)) as shown inFIG. 11.

The coefficient generators 30A, 30B, 30C, 30D sequentially output thefilter coefficients at the f_(SH). Of these the first coefficientgenerator 30A repeatedly generates the filter coefficients k₁₁, k₁₀, k₉,0 at the f_(SH) rate. The second coefficient generator 30B repeatedlygenerates the filter coefficients k₈, k₇, k₆, 0 at the f_(SH) rate,while the third coefficient generator 30C repeatedly generates thefilter coefficients k₅,k₄, k₃, 0 at the f_(SH) rate. The fourthcoefficient generator 30D repeatedly generates the filter coefficientsk₂,k₁, k₀, 0 at the f_(SH) rate.

The transversal filter 40 processes the data of the f_(SH) rategenerated by the interpolating circuit 20 with rate-converting filteringbased on the filter coefficients sequentially supplied by the fourcoefficient generators 30A, 30B, 30C, 30D.

This transversal filter 40 is a register postfix type or transposed typetransversal filter made up of four multipliers 41A, 41B, 41C and 41D,four delay circuits 42A, 42B, 42C and 42D and three additive units 43A,43B and 43C. The f_(SH) rate data generated by the interpolating circuit20 are supplied simultaneously to the four multipliers 41A, 41B, 41C and41D.

Of the multipliers 41A, 41B, 41C and 41D, the first multiplier 41A isrepeatedly supplied by the coefficient generator 30A with the filtercoefficients k₁₁, k₁₀, k₉, 0 at the f_(SH) rate, and multiplies thef_(SH) rate data generated by the interpolating circuit 20 with thefilter coefficients k₁₁, k₁₀, k₉, 0 at the f_(SH) rate. The outputproduct data of the first multiplier 41A is fed to the additive unit 43Avia the first delay circuit 42A.

The second multiplier 41B is repeatedly supplied by the coefficientgenerator 30B with the filter coefficients k₈, k₇, k₆, 0 at the f_(SH)rate, and multiplies the f_(SH) rate data generated by the interpolatingcircuit 20 with the filter coefficients k₈, k₇, k₆, 0 at the f_(SH)rate. The output product data of the second multiplier 41B is fed to thefirst additive unit 43A. The output sum data of the first additive unit43A is fed via the second delay circuit 42B to the second additive unit43B.

The third multiplier 41C is repeatedly supplied by the coefficientgenerator 30C with the filter coefficients k₆, k₄, k₃, 0 at the f_(SH)rate, and multiplies the f_(SH) rate data generated by the interpolatingcircuit 20 with the filter coefficients k₅, k₄, k₃, 0 at the f_(SH)rate. The output product data of the second multiplier 41C is fed to thesecond additive unit 43B. The output sum data of the second additiveunit 43B is fed via the third delay circuit 42C to the third additiveunit 43C.

The fourth multiplier 41D is repeatedly supplied by the coefficientgenerator 30D with the filter coefficients k₂, k₁, k₀, 0 at the f_(SH)rate, and multiplies the f_(SH) rate data generated by the interpolatingcircuit 20 with the filter coefficients k₂, k₁, k₀, 0 at the f_(SH)rate. The output product data of the fourth multiplier 41D is fed to thethird additive unit 43C. The output sum data of the third additive unit43C is fed via the fourth delay circuit 42D to the output terminal 50.

In the above-described transversal filter 40, the arithmetic-logicaloperation shown i FIG. 12 is executed, so that i=3m+1 data, convertedfrom the f_(SL) input data {X_(n) } into f_(SH) rate data, that is

    Y.sub.1 =k.sub.3 ·X.sub.3 +k.sub.7 ·X.sub.2 +k.sub.11 ·X.sub.1

    Y.sub.4 =k.sub.2 ·X.sub.4 +k.sub.6 ·X.sub.3 +k.sub.10 ·X.sub.2

    Y.sub.7 =k.sub.1 ·X.sub.5 +k.sub.5 ·X.sub.4 +k.sub.9 ·X.sub.3

    Y.sub.10 =k.sub.0 ·X.sub.6 +k.sub.4 ·X.sub.5 +k.sub.8 ·X.sub.4

    Y.sub.13 =k.sub.3 ·X.sub.6 +k.sub.7 ·X.sub.5 +k.sub.11 ·X.sub.4

    Y.sub.16 =k.sub.2 ·X.sub.7 +k.sub.6 ·X.sub.6 +k.sub.10 ·X.sub.5

    Y.sub.19 =k.sub.1 ·X.sub.8 +k.sub.5 ·X.sub.7 +k.sub.9 ·X.sub.6

    Y.sub.22 =k.sub.0 ·X.sub.9 +k.sub.4 ·X.sub.8 +k.sub.8 ·X.sub.7

    Y.sub.25 =k.sub.3 ·X.sub.9 +k.sub.7 ·X.sub.8 +k.sub.11 ·X.sub.7

    Y.sub.28 =k.sub.2 ·X.sub.10 +k.sub.6 ·X.sub.9 +k.sub.10 ·X.sub.8

are sequentially produced as output data {Y_(m) }.

The delay circuits 42A, 42B, 42C and 42D apply unit delay quantities atthe f_(SH) rate data to the f_(SH) rate data, and each comprise aD-flipflop performing a latch operation at the f_(SH) rate. The fourthdelay circuit 42D simply latches the f_(SH) rate output data {Y_(i) } atan output stage and is not indispensable in the resister postfix typetrasversal filter.

Since the multipliers 41A, 41B, 41C and 41D multiply filter coefficients0 with 0 data, the filter coefficient multiplied with the 0 data feednot necessarily be 0, while data multiplied by the filter coefficientsneed not necessarily be zero data.

With the present first embodiment, the input data {X_(n) } having a rateof f_(SL) (f_(SL) =13.5 MHz) are converted into output data {Y_(m) }having a rate of f_(SH) (f_(SH) =18 MHz) by N:M=3:4 up rate conversion,where M-N=1. It is possible with the rate converter of the presentinvention to effect up rate conversion of N:M (N<M) with M and N beingarbitrary coprime integers.

With the rate converter according to the present invention, describedabove, a 0 data is inserted at every N data of the f_(SL) rate inputdata {X_(n) } by the interpolating circuit, and the f_(SH) rate datagenerated by the interpolating circuit is filtered by a register postfixtype transversal filter for achieving up rate conversion of N:M (N<M)for generating f_(SH) rate output data from the f_(SL) rate input data{X_(n) }.

The transversal filter for performing such up conversion by sequentiallychanging over the filter coefficients at the output rate for filteringas proposed in JP Patent Kokai No.4-185774, may also be achieved using aconventional register-prefix transversal filter. However, a fastoperation may be realized using a fast process by employing a registerpost-fix type transversal filter as in the rate converter of the presentinvention.

The rate converter according to the present invention may also beconfigured as shown in the block diagram of FIG. 13.

In the second embodiment, shown in FIG. 13, the present invention isapplied to a down rate converter of performing 4:3 down rate conversionof converting input data {X_(m) } having a rate of f_(SH) (f_(SH) =18MHz) into output data {Y_(n) } having a rate of f_(SL) (f_(SL) =13.5MHz). The rate converter comprises a transversal filter 70 fed withf_(SH) rate input data {X_(m) } via an input terminal 60, fourcoefficient generators 80A, 80B, 80C and 80D for sequentially applyingfilter coefficients to the transversal filter 70, and a thinning circuit90 for thinning the f_(SH) rate data {Y_(i) }0 filtered by thetransversal filter 70 to the f_(SL) for outputting f_(SL) output data{Y_(m) } at an output terminal 95.

In the present second embodiment, the coefficient generators 80A, 80B,80C, 80D sequentially output the filter coefficients at the f_(SH). Ofthese the first coefficient generator 80A repeatedly generates thefilter coefficients k₉, k₁₀, k₁₁ at the f_(SH) rate. The secondcoefficient generator 80B repeatedly generates the filter coefficientsk₆, k₇, k₈ at the f_(SH) rate, while the third coefficient generator 80Crepeatedly generates the filter coefficients k₃, k₄, k₅ at the f_(SH)rate. The fourth coefficient generator 80D repeatedly generates thefilter coefficients k₀,k₁, k₂ at the f_(SH) rate.

The transversal filter 70 processes the f_(SH) rate input data {X_(m) }supplied thereto via the input terminal 60 by rate-converting filteringbased on the filter coefficients sequentially supplied from the fourcoefficient generators 80A, 80B, 80C and 80D.

This transversal filter 70 is a register postfix type or transposed typetransversal filter made up of four multipliers 71A, 71B, 71C and 71D,four delay circuits 72A, 72B, 72C and 72D and three additive units 73A,73B and 73C. The f_(SH) rate input data are supplied via the inputterminal 60 simultaneously to the four multipliers 71A, 71B, 71C and71D.

Of the multipliers 71A, 71B, 71C and 71D, the first multiplier 71A isrepeatedly supplied by the coefficient generator 80A with the filtercoefficients k₉, k₁₀, k₁₁ at the f_(SH) rate, and multiplies the f_(SH)rate input data {X_(m) } with the filter coefficients k₉, k₁₀, k₁₁ atthe f_(SH) rate. The output product data of the first multiplier 81A isfed to the additive unit 73A via the first delay circuit 72A.

The second multiplier 71B is repeatedly supplied by the coefficientgenerator 80B with the filter coefficients k₆, k₇, k₈ at the f_(SH)rate, and multiplies the f_(SH) rate input data {X_(m) } with the filtercoefficients k₆, k₇, k₈ at the f_(SH) rate. The output product data ofthe second multiplier 71B is fed to the first additive unit 73A. Theoutput sum data of the first additive unit 73A is fed via the seconddelay circuit 72B to the second additive unit 73B.

The third multiplier 71C is repeatedly supplied by the coefficientgenerator 80C with the filter coefficients k₃, k₄, k₅ at the f_(SH)rate, and multiplies the f_(SH) rate input data {X_(m) } with the filtercoefficients k₃, k₄, k₅ at the f_(SH) rate. The output product data ofthe second multiplier 41C is fed to the second additive unit 73B. Theoutput sum data of the second additive unit 73B is fed via the thirddelay circuit 72C to the third additive unit 73C.

The fourth multiplier 71D is repeatedly supplied by the coefficientgenerator 80D with the filter coefficients k₀, k₁, k₂ at the f_(SH)rate, and multiplies the f_(SH) rate input data {X_(m) } with the filtercoefficients k₀, k₁, k₂ at the f_(SH) rate. The output product data ofthe fourth multiplier 41D is fed to the third additive unit 73C. Theoutput sum data of the third additive unit 73C is outputted via thefourth delay circuit 72D.

The thinning circuit 90 executes thinning a f_(SH) rate filter outputdata {Y_(i) }0 of the transversal filter 70 to the f_(SL) rate toproduce=4n data {Y.sub.(4n) }, that is,

    Y.sub.0 =k.sub.1 ·X.sub.4 +k.sub.4 ·X.sub.3 +k.sub.7 ·X.sub.2 +k.sub.10 ·X.sub.1

    Y.sub.4 =k.sub.2 ·X.sub.5 +5.sub.4 ·X.sub.4 +k.sub.3 ·X.sub.3 +k.sub.11 ·X.sub.2

    Y.sub.3 =k.sub.0 ·X.sub.7 +k.sub.3 ·X.sub.6 +k.sub.6 ·X.sub.5 +k.sub.9 ·X.sub.4

    Y.sub.12 =k.sub.1 ·X.sub.8 +k.sub.4 ·X.sub.7 +k.sub.7 ·X.sub.6 +k.sub.10 ·X.sub.5

    Y.sub.16 =k.sub.2 ·X.sub.9 +k.sub.5 ·X.sub.3 +k.sub.8 ·X.sub.7 +k.sub.11 ·X.sub.6

    Y.sub.20 =k.sub.0 ·X.sub.11 +k.sub.3 ·X.sub.10 +k.sub.6 ·X.sub.9 +k.sub.9 ·X.sub.3

as output data {Y_(n) } converted from the f_(SH) rate input data intof_(SL) rate data, which are sequentially outputted at the outputterminal 95.

The delay circuits 72A, 72B, 72C and 72D apply unit delay quantities atthe f_(SH) rate data to the f_(SH) rate and each comprise a D-flipflopperforming a latch operation at the f_(SH) rate. The fourth delaycircuit 42D simply latches the f_(SH) rate output data {Y_(i) } at anoutput stage and is not indispensable in the register postfix typetrasversal filter.

With the present first embodiment, the input data {X_(n) } having a rateof f_(SH) (f_(SH) =18 MHz) are converted into output data {X_(m) }having a rate of f_(SL) (f_(SL) =13.5 MHz) by N:M=4:3 up rateconversion, where M-N=1. It is possible with the rate converter of thepresent invention to effect down rate conversion of N:M (N<M) with M andN being arbitrary coprime integers.

With the rate converter of the present invention, described above, thef_(SH) rate input data is filtered by a register postfix typetransversal filter and subsequently thinned by a thinning circuit forachieving down rate conversion of M:N (M>N) for generating f_(SL) outputdata {Y_(n) } from the f_(SH) rate input data {X_(m) }.

The transversal filter for filtering by sequentially changing over thefilter coefficients at an output rate may be implemented using anordinary register-prefix type transversal filter for down rateconversion, as proposed in JP Patent Kokai Publication 4-185774.However, a fast operation may be achieved using a fast process byemploying a register prefix type transversal filter as in the case ofthe rate converter according to the present invention.

The register prefix type transversal filters 40, 70 of the first andsecond embodiments are similarly configured to each other. In addition,the filter coefficients generated by the coefficient generators 30A to30D and 80A to 80D are the same coefficients except that the outputsequence is different. Thus the rate converter for bidirectional rateconversion may be simply implemented by employing a register prefix typetransversal filter in common.

FIG. 14 shows, in a block diagram, an arrangement of a digital camcorder having a bidirectional rate converter according to the presentinvention.

The digital cam corder according to a third embodiment of the presentinvention records imaging signals produced by an imaging unit 101 in adigital form as picture data pursuant to the D1 standard, and includesan analog/digital (A/D) converter 103 fed via an analog signal processor102 with three color imaging signals R(f_(s1)), G(f_(s1)) and B(f_(s1))produced by the imaging unit 101, a picture signal processor 104 fedwith the imaging data R, G and B digitized by the A/D converter 103, ananalog outputting signal processor 105 fed with two digital colordifference signals C_(R) (f_(s1)) and C_(B) (f_(s1)) and the digitalluminance signals Y(f_(s1)) generated by the picture signal processor104 and rate converting unit 108. A recording/reproducing unit 107 forrecording/reproduction of picture data pursuant to the D1 standard isconnected to the rate converting unit 106 over a bidirectional bus.

The imaging unit 101 separates the imaging light incident thereon froman imaging lens, not shown, via an optical low-pass filter, into threecolor components by a color-separating prism for imaging three colorimages of the object image by three CCD image sensors. These CCD imagesensors are driven at the f_(s1) rate so that the color imaging signalsR(f_(s1)), G(f_(s1)) and B(f_(s1)) are read at the f_(s1) rate. Thethree color imaging signals R(f_(s1)), G(f_(s1)) and B(f_(s1)), read outat the f_(s1) rate from the CCD image sensors, are fed via the analogsignal processor 102 to the A/D converter 103.

The imaging unit 101 is arranged in accordance with spatial pixelshifting system such that the CCD image sensors for imaging the red-huedpicture and the blue-hued picture are shifted in a horizontal directionby one-half the spatial pixel sampling period τ_(s) with respect to thegreen picture imaging CCD image sensor.

The analog signal processor 102 performs correlated dual sampling on thethree color imaging signals R(f_(s1)), G(f_(s1)) and B(f_(s1)) read outfrom the CCD image sensors of the imaging unit 101 for performing levelcontrol such as white balance or black balance.

The A/D converter 103 performs A/D conversion synchronized with drivingclocks having a pre-set phase at the f_(s1) rate equal to the samplingrate of the three color imaging signals R(f_(s1)), G(f_(s1)) andB(f_(s1)). The f_(s1) rate three color imaging signals R(f_(s1)),G(f_(s1)) and B(f_(s1)). digitized by the A/D converter 103 are fed tothe picture signal processor 104.

The picture signal processor 104 performs picture enhancement, pedestaladdition, non-linear processing, such as gamma or knee processing orlinear matrix processing on the three color imaging signals R(f_(s1)),G(f_(s1)) and B(f_(s1)) fed from the A/D converter 103, while performingmatrix processing for generating the two digital color differencesignals C_(R) (f_(s1)) and C_(B) (f_(s1)) and the digital luminancesignals Y(f_(s1)) from the three color imaging signals R(f_(s1)),G(f_(s1)) and B(f_(s1)).

The picture signal processor 104 performs well-known high resolutionprocessing corresponding to the spatial pixel shifting method in theimaging unit 101, with the clocks at the f_(s1) rate as master clocks,and generates the f_(s1) rate two digital color difference signals C_(R)(f_(s1)) and C_(B) (f_(s1)) and digital luminance signals Y(f_(s1)) fromthe three color imaging signals R(f_(s1)), G(f_(s1)) and B(f_(s1)). Theanalog signal outputting signal processor 105 functions as an analoginterface for the f_(s1) rate two digital color difference signals C_(R)(f_(s1)) and C_(B) (f_(s1)) and digital luminance signals Y(f_(s1))generated by the picture signal processor 104 or the rate convertingunit 108, and is made up of a digital encoder 105A and respectivedigital/analog converters 105B, 105C. The analog signal outputtingsignal processor 105 generates digital composite signals CS_(OUT)(2f_(s1)) and a digital monitor signal Y_(VF) (f_(s1)) by the digitalencoder 108A conforming to the usual NTSC or PAL system. The digitalcomposite signals CS_(OUT) (2f_(s1)) are converted into analog signalsby the D/A converter 108C for outputting a monitor signal Y_(VF) to befed to a view finder 109. On the other hand, the digital compositesignal CS_(OUT) (2f_(s1)) is converted by the D/A converter 105C intoanalog signals for outputting a composite video signal CS.

The rate converting processor 108 effects bidirectional rate conversionbetween the f_(s1) rate related data rate signals and the f_(s2) raterelated data rate signals. During the recording mode, the rateconverting unit 106 converts the f_(s1) rate related data rate signalsgenerated by the picture signal processor 104, that is, signalsY(f_(s1)), C_(R) (f_(s1) /2), C_(B) (f_(s1) /2) into the f_(s2) raterelated data rate signals Y(f_(s2)), C_(R) (f_(s2) /2), C_(B) (f_(s2)/2) which are fed to the recording/reproducing unit 107. During thereproducing mode, the rate converting unit 108 converts the f_(s2) raterelated data rate signals supplied by the recording/reproducing unit107, that is, signals Y(f_(s2)), C_(R) (f_(s2) /2), C_(B) (f_(s2) /2)into the f_(s1) rate related data rate signals Y(f_(s1)), C_(R) (f_(s1)/2), C_(B) (f_(s1) /2) which are fed to the analog signal outputtingsignal processor 105.

The rate converting processor 106 comprises a rate converting circuit106A for luminance signals and a rate converting circuit 106B for colordifference signals.

The rate converting circuit 108A for luminance signals i a bidirectionalrate converter according to the present invention and comprises a rateconverting block 120, a digital filter block 130 and a filtercoefficient generating block 140, as shown in the conceptual blockdiagram of FIG. 15.

In the conceptual block diagram of FIG. 15, a terminal 111 is a firstinput/output terminal connected over a bidirectional bus to the picturesignal processor 104 and the analog signal outputting signal processor105. To this first input/output terminal 111 are connected an input endof a line receiver 112 and an output end of a line driver 113. On theother hand, a terminal 114 is a second input/output terminal connectedover a bidirectional bus to the recording/reproducing unit 107. To thissecond input/output terminal 114 are connected an input end of a linereceiver 115 and an output end of a line driver 116.

To a first input terminal 120A of the rate converting block 120 areconnected respective output ends of the line receivers 112, 115 via achangeover switch 117. The changeover switch 117 is controlled by thecontrol signal supplied via a terminal 118 to select the output end ofthe line receiver 112 and the output end of the line receiver 115 duringthe recording mode and during the playback mode, respectively. Thus thefirst input terminal 120A of the rate converting block 120 is fed duringthe recording mode with the f_(s1) rate digital luminance signalsy(f_(s1)) from the picture signal processor 104 via the changeoverswitch 117, while being fed during the reproducing mode with the f_(s2)rate digital luminance signals y(f_(s2)) from the recording/reproducingunit 107 via the changeover switch 117.

The rate converting block 120 has its first output terminal 120Cconnected to an input terminal of the digital filter block 130, anoutput terminal of which is connected to the second input terminal 120Bof the rate converting block 120.

The rate converting block 120 has its second output terminal 120Dconnected to the first input/output terminal 111 via the line driver 113and to the second input/output terminal 114 via the line driver 116. Theline drivers 113, 116 are controlled by a control signal supplied viathe terminal 118 so that the line driver 115 is in the operative statewith the line driver 113 being inoperative during the recording mode andthe line driver 113 is in the operative state with the line driver 115being inoperative during the reproducing mode. Thus the converted outputof the second output terminal 120D of the rate converting bock 120 issupplied during the recording mode from the second input/output terminal114 to the recording/reproducing unit while being supplied during thereplay mode from the first input/output terminal 111 to the analogsignal outputting signal processor 105.

The rate converting block 120 is controlled by the control signalsupplied via the terminal 118 so that, during the recording mode, thef_(s1) rate (f_(s1) =18 MHz, for example) digital luminance signalY(f_(s1)) supplied from the picture signal processor 104 via thechangeover switch 117 to the first input terminal 120A is converted bythinning to the f_(s2) rate (f_(s2) =13.5 MHz, for example) digitalluminance signal Y(f_(s2)) pursuant to the D1 standard, and so that,during the replay mode, the f_(s2) rate (f_(s2) =13.5 MHz, for example)digital luminance signal Y(f_(s2)) pursuant to the D1 standard, suppliedfrom the recording/reproducing unit 107 via the changeover switch 117 tothe first input terminal 120A, is converted into the f_(s1) rate (f_(s1)=18 MHz, for example) digital luminance signal Y(f_(s1)).

The rate converting block 120 is made up of an interpolating circuit 121a thinning circuit 122, a clock generator 124, a first changeover switch125 and a second changeover switch 126, as shown for example in theblock diagram of FIG. 16.

The first changeover switch 125 selects signals outputted at the firstoutput terminal 120C and is controlled by a control signal supplied viaa terminal 118 for outputting the f_(s1) rate digital luminance signalY(f_(s1)) (f_(s1) =18 MHz) supplied at the input terminal 120A directlyat the first output terminal 120C during the recording mode, and foroutputting the f_(s1) rate digital luminance signal Y(f_(s1)) (f_(s1)=18 MHz) produced by interpolating the f_(s2) rate digital luminancesignal Y(f_(s2)) (f_(s2) =13.5 MHz) by the interpolating circuit 121.

The interpolating circuit 121 comprises first and second D flipflops121A, 121B, an AND gate 121C and an inverter 121D.

The first D flipflop 121A latches the f_(s2) rate digital luminancesignal Y(f_(s2)) (f_(s2) =13.5 MHz) supplied during the replay mode tothe first input terminal 120A with a data latch clock d-ck, having thetiming shown in FIG. 17, supplied from the clock generator 124. The ANDgate 121C ANDs the latch output data from the first D flipflop 121A andthe zero insertion data, having the timing of FIG. 17, supplied from theclock generator 124. The second D flipflop 121B latches the AND outputdata of the AND gate 121C by the latch clock having the f_(s1) rate(f_(s1) =18 MHz) at the timing shown in FIG. 17. The latch output dataof the second D flipflop 121B is the f_(s1) rate digital luminancesignal Y(f_(s1)) (f_(s1) =18 MHz).

The second changeover switch 126 selects signals outputted at the firstoutput terminal 120D and is controlled by a control signal supplied viathe terminal 118 for outputting the f_(s2) rate digital luminance signalY(f_(s2)) (f_(s2) =13.5 MHz) produced by thinning the f_(s1) ratedigital luminance signal Y(f_(s1)) (f_(s1) =18 MHz) supplied to thesecond terminal 120B by the thinning circuit 122 during the recordingmode and for outputting the f_(s1) rate digital luminance signalY(f_(s1)) (f_(s1) =18 MHz) supplied to the second input terminal 120B atthe second output terminal 120D during the replay mode.

The thinning circuit 122 comprises first and second D flipflops 122A,122B and generates the f_(s2) rate digital luminance signal Y(f_(s2))(f_(s2) =13.5 MHz) by latching the f_(s1) rate digital luminance signalY(f_(s1)) (f_(s1) =18 MHz) supplied to the second input terminal 120B bythe data latch clock d-ck of the timing shown in FIG. 18, supplied fromthe clock generator 124 by the first D flipflop 122A, and by re-latchingthe latch output data with the latch clock of the f_(s2) rate (f_(s2)=13.5 MHz) at the timing shown in FIG. 18.

The clock generator 124 comprises a divide-by-4 counter 124A forgenerating the zero insertion data Co and the coefficient address dataADR by counting the clocks ck-c of the f_(s1) rate (f_(s2) =18 MHz). Thedivide-by-4 counter 124A is reset by a reset signal rst generated onpower up or at the timing of the horizontal synchronization. Thedivide-by-4 counter 124A applies the generated coefficient address dataADR to the coefficient generating block.

The digital filter block 130 and the coefficient generating block 140are configured as shown for example in FIG. 19.

This digital filter block 130 is a register postfix type transversalfilter made up of four multipliers 131A, 131B, 131C and 131D, four delaycircuits 132A, 132B, 132C and 132D and three additive units 133A, 133Band 133C. An output of the rate converting block 120 is simultaneouslyapplied to the four multipliers 131A to 131D.

Of the multipliers 131A, 131B, 131C and 131D, the first multiplier 131Ais repeatedly supplied by the first coefficient generator 140A of thecoefficient, generating block 140 with the filter coefficientsrepeatedly supplied at the f_(s1) rate, and multiplies the output of therate converting block 120 with the filter coefficients. The outputproduct data of the first multiplier 131A is fed to the additive unit133A via the first delay circuit 132A.

The second multiplier 131B is repeatedly supplied by the secondcoefficient generator 140B of the coefficient generating block 140 withthe filter coefficients, repeatedly supplied at the f_(s1) rate, andmultiplies the output of the rate converting block 120 with the filtercoefficients. The output product data of the second multiplier 131B isfed to the first additive unit 133A, the sum output data of which is fedvia the second delay circuit 132B to the second additive unit 133B.

The third multiplier 131C is repeatedly supplied by the thirdcoefficient generator 140C of the coefficient generating block 140 withthe filter coefficients repeatedly, supplied at the f_(s1) rate, andmultiplies the output of the rate converting block 120 with the filtercoefficients. The output product data of the third multiplier 131C isfed to the second additive unit 133B, the sum output data of which isfed via the third delay circuit 132B to the third additive unit 133C.

The fourth multiplier 131D is repeatedly supplied by the fourthcoefficient generator 140D of the coefficient generating block 140 withthe filter coefficients repeatedly supplied at the f_(s1) rate, andmultiplies the output of the rate converting block 120 with the filtercoefficients. The output product data of the fourth multiplier 131D isfed to the third additive unit 133C, the sum output data of which is fedvia the fourth delay circuit 132D to the second input terminal 120B ofthe digital filter block 130.

The coefficient generating block 140 comprises four coefficientgenerators 141A, 141B, 141C and 141D.

The first coefficient generator 141A of the coefficient generating block140 has a coefficient memory 142A storing filter coefficients k₁₁, k₁₀,k₉, 0 and a selector 143A for selectively outputting the coefficientsk₁₁, k₁₀, k₉, 0 from the coefficient memory 142A. The selector 143Aexecutes its selecting operation responsive to the address data ADRsupplied from the divide-by-4 counter 124A of the clock generator 124and repeatedly outputs the filter coefficients k₁₁, k₁₀, k₉, 0 at thef_(s1) rate during the recording mode, while repeatedly outputting thefilter coefficients k₉, k₁₀, k₁₁ at the f_(s1) rate during the replaymode.

The second coefficient generator 141B has a coefficient memory 142B forstoring filter coefficients k₈, k₇, k₆, 0 and a selector 143B forselectively outputting the coefficients k₈, k₇, k₉, 0 from thecoefficient memory 142B. The selector 143B executes its selectingoperation responsive to the address data ADR supplied from thedivide-by-4 counter 124A of the clock generator 124 and repeatedlyoutputs the filter coefficients k₈, k₇, k₆, 0 at the f_(s1) rate duringthe recording mode, while repeatedly outputting the filter coefficientsk₆, k₇, k₈ at the f_(s1) rate during the replay mode.

The third coefficient generator 141C has a coefficient memory 142C forstoring filter coefficients k₅, k₄, k₃, 0 and a selector 143C forselectively outputting the coefficients k₅, k₄, k₃, 0 from thecoefficient memory 142C. The selector 143C executes its selectingoperation responsive to the address data ADR supplied from thedivide-by-4 counter 124A of the clock generator 124 and repeatedlyoutputs the filter coefficients k₅, k₄, k₃, 0 at the f_(s1) rate duringthe recording mode, while repeatedly outputting the filter coefficientsk₃, k₄, k₁ at the f_(s1) rate during the replay mode.

The fourth coefficient generator 141D of the coefficient generatingblock 140 has a coefficient memory 142C for storing filter coefficientsk₂, k₁, k₀, 0 and a selector 143C for selectively outputting thecoefficients k₂, k₁, k₀, 0 from the coefficient memory 142D. Theselector 145D executes its selecting operation responsive to the addressdark ADR supplied from the divide-by-4 counter 124A of the clockgenerator 124 and repeatedly outputs the filter coefficients k₂, k₁, k₀,0 at the f_(s1) rate during the recording mode, while repeatedlyoutputting the filter coefficients k₀, k₁, k₂ at the f_(s1) rate duringthe replay mode.

The rate converting circuit 106B for color difference signals is fedwith f_(s1) rate digital color difference signals C_(R) (f_(s1)), C_(B)(f_(s1)) after being lowered to the f_(s1) /2 rate by 1/2 sepdowncircuits 108A, 108B and arrayed dot-sequentially by a multiplexor 108C,that is as a f_(s1) rate digital dot-sequential color difference signalC_(R) /C_(B) (f_(s1)). The rate converting circuit 106B down-convertsthe rate of the signal into a f_(s2) rate digital dot-sequential colordifference signal C_(R) /C_(B) (f_(s2)).

During the replay mode, the f_(s2) rate digital dot-sequential colordifference signal C_(R) /C_(B) (f_(s2)) is up rate converted into thef_(s1) rate digital dot-sequential color difference signal C_(R) /C_(B)(f_(s1)). Thus the present rate, conversion circuit 106B for the colordifference signals ia a bidirectional rate converter according to thepresent invention and, as a principle, performs rate conversion similarto that performed by the above-described rate conversion circuit 106Yfor luminance signals.

The f_(s1) rate digital dot-sequential color difference signal C_(R)C_(B) (f_(s1)), produced by the rate conversion circuit 106B for colordifference signals, is rendered parallel by the digital multiplexor 108Dand thus converted into f_(s1) /2 rate digital color difference signalsC_(R) (f_(s1) /2), C_(B) (f_(s1) /2), which then are doubled in rate bydoublers 108E, 108F into f_(s1) rate digital color difference signalsC_(R) (f_(s1)), C_(B) (f_(s1)) which are supplied to the digital encoder105A of the signal processor 105.

The rate converter according to the present invention is configured asshown in the block diagram of FIG. 20.

With the fourth embodiment, shown in FIG. 20, the present invention isapplied to a 3:5 up rate converter for converting the f_(SL) rate inputdata {X_(n) } into f_(SH) rate output data {Y_(m) }. The rate convertercomprises an interpolating circuit 220 for interpolating the f_(SL) rateinput data {X_(n) }, entered via an input terminal 210, for generatingthe f_(SH) rate data, five coefficient generators 230A, 230B, 230C, 230Dand 230E for outputting respective filter coefficients and a transversalfilter 240 for filtering the f_(SH) rate data generated by theinterpolation circuit 220 based on the above-mentioned filtercoefficients for outputting the f_(SH) rate output data {Y_(m) } at anoutput terminal 240.

The interpolation circuit 220 inserts two 0 data for every five data ofthe f_(SL) rate input data {X_(n) } entered at the input terminal 210for generating f_(SH) data.

The coefficient generators 230A, 230B, 230C, 230D and 230E sequentiallyoutput respective filter coefficients at the f_(SH) rate. Thus the firstcoefficient generator 230A repeatedly generates filter coefficients k₀,k₂, 0, k₁, 0 at the f_(SH) rate, while the second coefficient generator230B repeatedly generates filter coefficients k₃, k₅, 0, k₄, 0 at thef_(SH) rate. The third coefficient generator 230C repeatedly generatesfilter coefficients k₆, k₈, 0, k₇, 0 at the f_(SH) rate, while thefourth coefficient generator 230D repeatedly generates filtercoefficients k₃, k₁₁, 0, k₁₀, 0 at the f_(SH) rate. The fifthcoefficient generator 230E repeatedly generates filter coefficients k₁₂,k₁₄, 0, k₁₃, 0 at the f_(SH) rate.

The transversal filter 240 processes the f_(SH) rate data generated bythe interpolation circuit 220 by rate-converting filtering based on thefilter coefficients sequentially supplied from the four coefficientgenerators 230A, 230B, 230C and 230D. This transversal filter 230 is aregister postfix type transversal filter made up of five multipliers241A, 241B, 241C, 241D and 241E, five delay circuits 242A, 242B, 242C,242D and 242E and four additive units 243A, 243B, 243C and 243D. Thef_(SH) rate input data, generated by the interpolation circuit 220, aresimultaneously supplied to the five multipliers 241A, 241B, 241C, 241Dand 241E.

Of the multipliers 241A, 241B, 241C, 241D and 241E, the first multiplier241A is repeatedly supplied by the coefficient generator 230A with thefilter coefficients k₀, k₂, 0, k₁, 0 at the f_(SH) rate, and multipliesthe f_(SH) rate data generated by the interpolating circuit 220 with thefilter coefficients k₀, k₂, 0, k₁, 0 at the f_(SH) rate. The outputproduct data of the first multiplier 241A is fed to the additive unit243A via the first delay circuit 242A.

The second multiplier 241B is repeatedly supplied by the coefficientgenerator 230B with the filter coefficients k₃, k₅, 0, k₄, 0 at thef_(SH) rate, and multiplies the f_(SH) rate data generated by theinterpolating circuit 220 with the filter coefficients k₃, k₄, 0, k₄, 0at the f_(SH) rate. The product output data of the second multiplier241B is fed to the first additive unit 243A. The sum output data of thefirst additive unit 243A is fed via the second delay circuit 242B to thesecond additive unit 243B.

The third multiplier 241C is repeatedly supplied by the coefficientgenerator 230C with the filter coefficients k₆, k₈, 0, k₇, 0 at thef_(SH) rate, and multiplies the f_(SH) rate data generated by theinterpolating circuit 220 with the filter coefficients k₆, k₈, 0, k₇, 0at the f_(SH) rate. The product output data of the third multiplier 241Cis fed to the second additive unit 243B. The sum output data of thesecond additive unit 243B is fed via the third delay circuit 242C to thethird additive unit 243C.

The fourth multiplier 241D is repeatedly supplied by the coefficientgenerator 230D with the filter coefficients k₉, k₁₁, 0, k₁₀, 0 at thef_(SH) rate, and multiplies the f_(SH) rate data generated by theinterpolating circuit 220 with the filter coefficients k₉, k₁₁, 0, k₁₀,0 at the f_(SH) rate. The product output data of the fourth multiplier241D is fed to the third additive unit 243D. The sum output data of thethird additive unit 243C is fed via the fourth delay circuit 242D to thefourth additive unit 243D.

The fifth multiplier 241E is repeatedly supplied by the coefficientgenerator 230E with the filter coefficients k₁₂, k₁₄, 0, k₁₃, 0 at thef_(SH) rate, and multiplies the f_(SH) rate data generated by theinterpolating circuit 220 with the filter coefficients k₁₂, k₁₄, 0, k₁₃,0 at the f_(SH) rate. The product output data of the fifth multiplier241E is fed to the fourth additive unit 243D. The sum output data of thefourth additive unit 243A is fed via the fifth delay circuit 242E to thefifth additive unit 243E.

At an output terminal 250 of the above-described transversal filter 240,i=3m+1 data {Y_(i) }, that is

    Y.sub.1 =k.sub.0 ·X.sub.1 +k.sub.5 ·X.sub.2 +0·0+k.sub.10 ·X.sub.3 +0·0

    Y.sub.4 =k.sub.2 ·X.sub.2 +0·0+k.sub.7 ·X.sub.3 +0·0+k.sub.12 ·X.sub.4

    Y.sub.7 =0·0+k.sub.4 ·X.sub.3 +0·0+k.sub.9 ·X.sub.4 +k.sub.14 ·X.sub.5

    Y.sub.10 =k.sub.1 ·X.sub.3 +0·0+k.sub.6 ·X.sub.4 +k.sub.11 ·X.sub.5 +0·0

    Y.sub.13 =0·0+k.sub.3 ·X.sub.4+k.sub.3 ·X.sub.5 +0·0+k.sub.13 ·X.sub.6

    Y.sub.16 =k.sub.0 ·X.sub.4 +k.sub.5 ·X.sub.5 0·0+k.sub.10 ·X.sub.6 +0·0

    Y.sub.19 =k.sub.2 ·X.sub.5 +·0+k.sub.7 ·X.sub.6 +0·0+k.sub.12 ·X.sub.7

are produced sequentially as output data {Y_(m) } converted from thef_(SL) input data {X_(n) } by rate conversion to the f_(SH) rate.

The output data {Y_(m) } produced at the output terminal 250 isequivalent to f_(SH) rate data (f_(SH) =5/3 f_(SL)) generated byfiltering 5 f_(SL) rate data, generated by inserting four 0s betweendata of the f_(SL) rate input data {X_(n) }, by a transversal filteroperating at the 5 f_(SL) rate, and extracting every third data.

The delay circuits 242A, 242B, 242C, 242D and 242E apply unit delayquantities at the f_(SH) rate data to the f_(SH) rate data andrespectively comprise D-flipflops performing a latch operation at thef_(SH) rate. The fifth delay circuit 242E simply latches the f_(SH) rateoutput data {Y_(i) } at an output stage and is not indispensable in theregister postfix type trasversal filter.

On the other hand, since the multipliers 241A, 241B, 241C, 241D and 241Emultiply 0 data with the filter coefficients 0, the filter coefficientsby which the 0 data is multiplied need not necessarily be 0, while databy which the filter coefficient 0 is multiplied need not necessarily be0 data.

With the present fourth embodiment, N:M=3:5 up rate conversion iscarried out with M-N=2. However, an up rate conversion by N:M, whereN<M, may also be performed, with M-N being an arbitrary integer.

Thus, with the rate converter of the present invention, it is possibleto achieve up rate conversion of N:M, where N<M, by inserting (M-0) 0data at every N data of the f_(SL) rate input data {X_(n) } by aninterpolation circuit, for generating f_(SH) rate data, and by filteringthe f_(SH) data generated by the interpolation circuit by a registerpostfix type transversal filter.

The rate converter according to the present invention is configured asshown in the block diagram of FIG. 21.

With the fifth embodiment, shown in FIG. 21, the present invention isapplied to a 5:3 down rate converter for converting the f_(SH) rateinput data {X_(m) } into f_(SL) rate output data {Y_(n) }. The rateconverter comprises transversal filter 270 having its input terminal 260supplied with the f_(SH) rate input data, five coefficient generators280A, 280B, 280C, 280D and 280E for outputting respective filtercoefficients to the transversal filter 270, and a thinning circuit 290for thinning the f_(SH) rate data {Y_(i) } filtered by the transversalfilter 270 to the f_(SL) rate for outputting f_(SL) output data {Y_(m) }at an output terminal

In the present fifth embodiment, the coefficient generators 280A, 280B,280C, 280D and 280E sequentially output the filter coefficients at thef_(SH) rate. Of these, the first coefficient generator 280A repeatedlygenerates the filter coefficients k₀, 0, k₁, 0, k₂ at the f_(SH) rate.The second coefficient generator 280B repeatedly generates the filtercoefficients k₅, k₃, 0, k₄, 0 at the f_(SH) rate, while the thirdcoefficient generator 280C repeatedly generates the filter coefficients0, k₈, k₆, 0, k₇ at the f_(SH) rate. The fourth coefficient generator280D repeatedly generates the filter coefficients k₁₀, 0, k₁₁, k₉, 0 atthe f_(SH) rate, while the fifth coefficient generator 280E repeatedlygenerates the filter coefficients 0, k₁₃, 0, k₁₄, k₁₂ at the f_(SH)rate.

The transversal filter 270 processes the f_(SH) rate input data {X_(m) }input data, supplied thereto via the input terminal 280, byrate-converting filtering, based on the filter coefficients sequentiallysupplied from the five coefficient generators 280A, 280B, 280C, 280D and280E. This transversal filter 270 is a register postfix type ortransposed type transversal filter made up of five multipliers 271A,271B, 271C, 271D and 271E, five delay circuits 272A, 272B, 272C, 272Dand 272E and four additive units 273A, 273B, 273C and 273D. The f_(SH)rate input data are supplied via the input terminal 280 simultaneouslyto the five multipliers 271A, 271B, 271C, 271D and 271E.

Of the multipliers 271A, 271B, 271C, 271D and 271E, the first multiplier271A is repeatedly supplied by the coefficient generator 280A with thefilter coefficients k₀, 0, k₁ , 0, k₂ at the f_(SH) rate, and multipliesthe f_(SH) rate input data {X_(m) } with the filter coefficients k₀ , 0,k₁, 0, k₂ at the f_(SH) rate. The output product data of the firstmultiplier 271A is fed to the additive unit 273A via the first delaycircuit 272A.

The second multiplier 271B is repeatedly supplied by the coefficientgenerator 280B with the filter coefficients k₅, k₃, 0, k₄, 0 at thef_(SH) rate, and multiplies the f_(SH) rate input data {X_(m) } with thefilter coefficients k₅, k₃, 0, k₄, 0 at the f_(SH) rate. The outputproduct data of the second multiplier 271B is fed to the first additiveunit 273A. The output sum data of the first additive unit 273A is fedvia the second delay circuit 272B to the second additive unit 273B.

The third multiplier 271C is repeatedly supplied by the coefficientgenerator 280C with the filter coefficients 0, k₈, k₆, 0, k₇ at thef_(SH) rate, and multiplies the f_(SH) rate input data {X_(m) } with thefilter coefficients 0, k₈, k₆, 0, k₇ at the f_(SH) rate. The outputproduct data of the third multiplier 271C is fed to the second additiveunit 273B. The output sum data of the second additive unit 273B is fedvia the third delay circuit 272C to the second additive unit 273C.

The fourth multiplier 271D is repeatedly supplied by the coefficientgenerator 280D with the filter coefficients k₁₀, 0, k₁₁, k₉, 0 at thef_(SH) rate, and multiplies the f_(SH) rate input data {X_(m) } with thefilter coefficients k₁₀, 0, k₁₁, k₉, 0 at the f_(SH) rate. The outputproduct data of the fourth multiplier 271D is fed to the third additiveunit 273C. The output sum data of the third additive unit 273C is fedvia the fourth delay circuit 272D to the fourth additive unit 273D.

The fifth multiplier 271E is repeatedly supplied by the coefficientgenerator 280E with the filter coefficients 0, k₁₃, 0, k₁₄, k₁₂ at thef_(SH) rate, and multiplies the f_(SH) rate input data {X_(m) } with thefilter coefficients 0, k₁₃, 0, k₁₄, k₁₂ at the f_(SH) rate. The outputproduct data of the fourth multiplier 271D is fed to the fourth additiveunit 273D. The output sum data of the fourth additive unit 273D isoutputted via the fifth delay circuit 272E.

The thinning circuit 290 thins the f_(SH) rate filter output data of thetransversal filter 270 to the f_(SL) rate to produce i=5n+1 data {Y_(i)}, that is,

    Y.sub.1 =k.sub.0 ·X.sub.1 +k.sub.3 ·X.sub.2 +k.sub.6·X.sub.3 +k.sub.9 ·X.sub.4 +k.sub.12 ·X.sub.5

    Y.sub.6 =k.sub.1 ·X.sub.3 +k.sub.4 ·X.sub.4 +k.sub.7·X.sub.5 +k.sub.10 ·X.sub.6 +k.sub.13 ·X.sub.7

    Y.sub.11 =k.sub.2 ·X.sub.5 +k.sub.5 ·X.sub.6 +k.sub.8 X.sub.6 +k.sub.11 ·X.sub.7 +k.sub.14 ·X.sub.3

    Y.sub.16 =k.sub.0 ·X.sub.6 +k.sub.3 ·X.sub.7 +k.sub.6·X.sub.8 +k.sub.9 ·X.sub.9 +k.sub.12 ·X.sub.10

as output data {Y_(n) } converted from the f_(SH) rate input data {X_(m)} into the f_(SL) rate, where data are sequentially outputted at theoutput terminal 295.

The output data {Y_(n) } produced at the output terminal 295 isequivalent to f_(SL) rate data (f_(SL) =3/5 f_(SH)) generated byfiltering 3 f_(SL) rate data, generated by inserting four 0s betweendata of the f_(SH) rate input data {X_(m) }, by a transversal filteroperating at the 5 f_(SH) rate, and extracting every third data.

The delay circuits 272A, 272B, 272C, 272D and 272E apply unit delayquantities at the f_(SH) rate data to the f_(SL) rate data andrespectively comprise D-flipflops performing a latch operation at thef_(SH) rate. The fifth delay circuit 242E simply latches the f_(SH) rateoutput data {Y_(i) } at an output stage and is not indispensable in theresister postfix type trasversal filter.

With the present fifth embodiment, N:M=5:3 down rate conversion iscarried out, where M-0=2. However, a down rate conversion by M:N, whereM>N, may also be Performed, with M-N being an arbitrary integer.

With the rate converter of the present invention, described above, thef_(SH) rate input data {X_(m) } is filtered by a register postfix typetransversal filter and subsequently thinned by a thinning circuit forachieving down rate conversion of M:N (M>N) for generating f_(SL) rateoutput data {Y_(n) } from the f_(SH) rate input data {X_(m) }.

The register postfix type transversal filters 240, 270 of the rateconverters of the fourth and fifth embodiments are similarly configuredto each other. In addition, the filter coefficients generated by thecoefficient generators 230A to 230E and 280A to 280E are the samecoefficients except that the output sequence is different. Thus the rateconverter for bidirectional rate conversion may be simply implemented byemploying a register prefix type transversal filter in common.

FIG. 22 shows, in a block diagram, an arrangement of a bidirectionalrate converter according to the present invention.

In the sixth embodiment, shown in FIG. 22, the present invention isapplied to a bidirectional rate converter for performing a N:M (N<M) uprate conversion of converting the f_(SL) rate input data {X_(n) } intof_(SH) rate output data {Y_(m) } and a M:N (M>N) down rate conversion ofconverting the f_(SH) rate input data {X_(m) } into f_(SL) rate outputdata {Y_(n) }. The rate converter of the present embodiment comprises arate conversion block 320, a digital filter block 330 and a filtercoefficient generating block 340.

The rate converter has a first input/output terminal 311 connected to abidirectional bus for transmitting the f_(SH) rate data and a secondinput/output terminal 312 connected to a bidirectional bus fortransmitting the f_(SL) rate data. An input end of the line receiver 312and an output end of a line driver 313 are connected to the firstinput/output terminal 311, while an input end of a line receiver 315 andan output end of a line driver 316 are connected to the secondinput/output terminal 314.

The rate converting block 320 has first and second input terminals 320A,320B and first and second output terminals 320C, 320D.

To the first input terminal 320A of the rate converting block 320A ofthe rate converting block 320, output ends of the line receivers 312,315 are connected via a changeover switch 317. The changeover switch 317is controlled by a control signal supplied via a terminal 318 forselecting the output end of the line receiver 312 during the down rateconversion mode and for selecting the output end of the line receiver315 during the up rate conversion mode. This causes the f_(SH) rateinput data {X_(m) } to be supplied from the first input/output terminal311 via the changeover switch 317 during the down rate conversion mode,while causing the f_(SL) rate input data {X_(n) } to be supplied fromthe second input/output terminal 314 via the changeover switch 317during the up rate conversion mode.

The rate conversion block 320 has its first output terminal 320Cconnected to an input terminal of the digital filter block 330, anoutput terminal of which is connected to the second input terminal 320Bof the rate converting block 320.

The second output terminal 320D of the rate converting block 320 isconnected via the line driver 313 to the first input/output terminal311, while being connected to the second input/output terminal 314 viathe line driver 316. The line drivers 313, 316 are controlled by thecontrol signal supplied via the terminal 318 so that the line driver 315becomes operative wit the line driver 313 remaining inoperative and theline driver 313 becomes operative with the line driver 315 remaininginoperative during the down rate conversion mode and during the up rateconversion mode, respectively. Thus the converted output data {Y_(n) }of the f_(SL) obtained at the second output terminal 320D of the rateconversion block 320 is outputted at the second output terminal 314during the down rate conversion mode, while the converted output data{Y_(m) } of the f_(SH) rate is outputted at the first input/outputterminal 311 during the up rate conversion mode.

The rate conversion block 320 is controlled by the control signalsupplied via the terminal 318 so as to perform thinning during the downrate conversion mode for converting the f_(SH) rate input data {X_(m) }supplied to the first input terminal 320A from the first input/outputterminal 311 via the changeover switch 317 into f_(SL) rate output data{Y_(n) }, and so as to perform interpolation during the up rateconversion mode for converting the f_(SL) rate input data {X_(n) }supplied to the first input terminal 320A from the first input/outputterminal 311 via the changeover switch 317 into f_(SH) rate output data{Y_(m) }.

Referring to the block diagram of FIG. 23, the rate converting block 320includes a FIFO memory 321, a write address generator 322 for applying awrite address w-adr to the FIFO memory 321 and a readout addressgenerator 323 for applying the readout address r-adr to the FIFO memory321. The rate converting block also includes a switch 324 for changingover the write clock w-ck and the readout clock r-ck applied to the FIFOmemory 321, and a changeover switch 325 for selectively connecting thefirst input terminal 320A and the second input terminal 320B to the datainput terminal of the FIFO memory 321.

The rate converting block further includes a changeover switch 326 forselectively connecting the first input terminal 320A and a data outputend of the FIFO memory 321 to the first output terminal 320C and achangeover switch 327 for selectively connecting the second inputterminal 320B and the data output end of the FIFO memory 321 to thefirst output terminal 320C.

During the down rate conversion mode, the changeover switch 324 changesover the f_(SL) rate clock NCK to the f_(SH) rate clock M_(CK) and viceversa for applying the f_(SH) rate clock M_(CK) as the write clock w-ckto the FIFO memory 321 and the write address generator 322 and forapplying the f_(SL) rate clock N_(CK) as the readout clock r-adr to theFIFO memory 321 and the readout address generator 323, while applyingthe f_(SL) rate clock N_(CK) as the write clock w-ck to the FIFO memory321 and the write address generator 322 and for applying the f_(SH) rateclock M_(CK) as the readout address r-adr to the FIFO memory 321 and thereadout address generator 323.

The changeover switches 325, 328, 327 execute the following changeoveroperations.

That is, during the down rate conversion mode, the changeover switch 325selects the second input terminal 320B, while the changeover switch 326selects the first input terminal 320A and the changeover switch 327selects the data output terminal of the FIFO memory 321. During the downrate conversion mode, the changeover switch 325 selects the first inputterminal 320A, while the changeover switch 328 selects the data outputterminal of the FIFO memory 321 and the changeover switch 327 selectsthe first input terminal 320B.

With the above-described rate converting block 320, the f_(SH) rateinput data {X_(m) } is supplied during the down rate conversion modefrom the first output terminal 320C via the changeover switch 328 to thedigital filter block 330, and the f_(SH) rate data {Y_(i) } supplied viathe digital filter block 330 to the second input terminal 320B issupplied via the changeover switch 325 to the data input terminal of theFIFO memory 321. The f_(SH) rate data {Y_(i) } is written in the FIFOmemory 321 in accordance with the write address w-adr generated by thewrite address generator 322 based on the f_(SH) rate write clock w-ck,while being read out as the f_(SL) rate output data {Y_(n) } from theFIFO memory 321 in accordance with the read address r-adr generated bythe read address generator 323 based on the f_(SL) rate readout clockr-ck. That is, thinning is carried out by reading by skipping addressesfor unnecessary (M-N) data of the M data contained in the f_(SH) ratedata {Y_(i) } for outputting f_(SL) output data {Y_(n) } at the secondoutput terminal 320D.

During the up rate conversion mode, the f_(SL) rate input data {X_(n) }supplied to the first input terminal 320A is written in the FIFO memory321 in accordance with the write address w-adr generated by the writeaddress generator 322 based on the f_(SL) rat write cock w-ck, and isread out from the FIFO memory 321 in accordance with the read addressr-adr generated by the read address generator 323 based on the f_(SL)rate read clock r-ck, for conversion into f_(SH) rate data, which issupplied from the first output terminal 320C to the digital filter block330. That is, interpolation is performed in place of zero insertion byreading out (M-N) data of N data of the input data {X_(n) } written inthe FIFO memory 321 from the same address for generating f_(SH) ratedata which is supplied to the digital filter block 330. The f_(SH) rateoutput data {Y_(i) } supplied via the digital filter block 330 to thesecond input terminal 320B is outputted to the second output terminal320D as output data {Y_(m) } via the second changeover switch 327.

The digital filter block 330 and the coefficient generating block 340are configured as shown for example in FIG. 24.

This transversal filter 330 is a register postfix type transversalfilter made up of five multipliers 331A, 331B, 331C, 331D and 331E, fivedelay circuits 332A, 332B, 332C, 332D and 332E and four additive units333A, 333B, 333C and 333D. The output data, generated by the rateconversion block 120, are simultaneously supplied to the fivemultipliers 331A, 331B, 331C, 331D and 331E.

Of the multipliers 331A, 331B, 331C, 331D and 331E, the first multiplier331A multiplies the output of the rate converting block 320 with thefilter coefficients repeatedly supplied thereto at the f_(SH) rate bythe first coefficient generator 340A of the coefficient generating block340. The product output data of the first multiplier 331A is suppliedvia the first delay circuit 332A to the first additive unit 333A.

The second multiplier 331B multiplies the output of the rate convertingblock 320 with the filter coefficients repeatedly supplied thereto atthe f_(SH) rate by the second coefficient generator 341B of thecoefficient generating block 340. The output product data of the secondmultiplier 331B is fed to the first additive unit 333A. The sum outputdata of the first additive node 333A is fed via the second delay circuit332B to the second additive node 333B.

The third multiplier 331C multiplies the output of the rate convertingblock 320 with the filter coefficients repeatedly supplied thereto atthe f_(SH) rate by the second coefficient generator 341C of thecoefficient generating block 340. The output product data of the thirdmultiplier 331C is fed to the second additive unit 333B. The sum outputdata of the second additive node 333B is fed via the third delay circuit332C to the third additive node 333C.

The fourth multiplier 331D multiplies the output of the rate convertingblock 320 with the filter coefficients repeatedly supplied thereto atthe f_(SH) rate by the fourth coefficient generator 341C of thecoefficient generating block 340. The output product data of the fourthmultiplier 331D is fed to the third additive unit 333C. The sum outputdata of the fourth additive node 333D is fed via the fourth delaycircuit 332D to the fourth additive node 333D.

The fifth multiplier 331E multiplies the output of the rate convertingblock 320 with the filter coefficients repeatedly supplied thereto atthe f_(SH) rate by the fifth coefficient generator 341E of thecoefficient generating block 340. The output product data of the fifthmultiplier 331E is fed to the fourth additive unit 333D. The sum outputdata of the fourth additive node 333A is fed via the fifth delay circuit332E to the second input terminal 320B of the digital filter block 330as a filter output.

The coefficient generating block 340 comprises five coefficientgenerators 341A, 341B, 341C, 341D and 341D.

The first coefficient generator 341A of the coefficient generating block340 has a coefficient memory 342A for storing filter coefficients k₀,k₁, k₂, 0 and a selector 343A for selectively outputting thecoefficients k₀, k₁, k₂, 0 from the coefficient memory 342A. Theselector 343A executes its selecting operation responsive to the addressdata ADR supplied from an address generator, not shown, and repeatedlyoutputs the filter coefficients k₀, 0, k₁, 0 and k₂, at the f_(SH) rateduring the down rate conversion mode, while repeatedly outputting thefilter coefficients k₀, k₂, 0, k₁, 0 at the f_(SH) rate during the uprate conversion mode.

The second coefficient generator 341B has a coefficient memory 342B forstoring filter coefficients k₃, k₄, k₅, 0 and a selector 343B forselectively outputting the coefficients k₃, k₄, k₆, 0 from thecoefficient memory 342B. The selector 343B executes its selectingoperation responsive to the address data ADR supplied from an addressgenerator, not shown, and repeatedly outputs the filter coefficients k₅,k₃, 0, k₄, 0 at the f_(SH) rate during the down rate conversion mode,while repeatedly outputting the filter coefficients k₃, k₅, 0, k₄, 0 atthe f_(SH) rate during the up rate conversion mode.

The third coefficient generator 341C has a coefficient memory 342C forstoring filter coefficients k₆, k₇, k₈, 0 and a selector 343C forselectively outputting the coefficients k₆, k₇, k₈, 0 from thecoefficient memory 342C. The selector 343C executes its selectingoperation responsive to the address data ADR supplied from an addressgenerator, not shown, and repeatedly outputs the filter coefficients 0,k₈, k₆, 0, k₇ at the fast rate during the down rate conversion mode,while repeatedly outputting the filter coefficients k₆, k₈, 0, k₇, 0 atthe f_(SH) rate during the up rate conversion mode.

The fourth coefficient generator 341D has a coefficient memory 342D forstoring filter coefficients k₉, k₁₀, k₁₁, 0 and a selector 343D forselectively outputting the coefficients k₉, k₁₀, k₁₁, 0 from thecoefficient memory 342D. The selector 343D executes its selectingoperation responsive to the address data ADR supplied from an addressgenerator, not shown, and repeatedly outputs the filter coefficientsk₁₀, 0, k₁₁, k₉, 0 at the f_(SH) rate during the down rate conversionmode, while repeatedly outputting the filter coefficients k₉, k₁₁, 0,k₁₀, 0 at the f_(SH) rate during the up rate conversion mode.

The fifth coefficient generator 341E has a coefficient memory 342E forstoring filter coefficients k₁₂, k₁₃, k₁₄, 0 and a selector 343E forselectively outputting the coefficients k₁₂, k₁₃, k₁₄, 0 from thecoefficient memory 342E. The selector 343E executes its selectingoperation responsive to the address data ADR supplied from an addressgenerator, not shown, and repeatedly outputs the filter coefficients 0,k₁₃, 0, k₁₄, k₁₂ at the f_(SH) rate during the down rate conversionmode, while repeatedly outputting the filter coefficients k₁₂, k₁₄, 0,k₁₃, 0 at the f_(SH) rate during the up rate conversion mode.

With the above-described rate converter, the f_(SL) rate convertedoutput data {Y_(n) } can be outputted via the second input/outputterminal 314 during the down rate conversion mode by executing 5:3 downrate conversion by performing thinning by the rate conversion block 320for filtering the f_(SH) rate input data {X_(m) } supplied to the firstinput/output terminal 311 by the digital filter block 330 for convertingthe input data into f_(SL) rate output data {Y_(n) }. On the other hand,the f_(SL) rate converted output data {Y_(m) } can be outputted via thesecond input/output terminal 314 during the up rate conversion mode byexecuting 3:5 up rate conversion by performing interpolation by the rateconversion block 320 for converting the f_(SL) rate input data {X_(n) }supplied via the first input terminal 311 and by filtering by thedigital filter block 330.

What is claimed is:
 1. A rate converter for converting an f_(s1) inputdata rate of an input signal to an f_(sh) output data rate, wherein saidinput data rate f_(s1) and said output data rate f_(sh) are in an N:Mconversion ratio with each other, with N and M being integers,comprising:interpolating means for interpolating said input signal byinserting (M-N) 0 data at every Nth interval of said input signal,thereby imparting said input signal with said f_(sh) output data rate; apostfix type transversal filter comprising:coefficient generating meansfor generating M sequences of respective filter coefficients, saidrespective filter coefficients in each sequence generated at the f_(sh)output data rate; multiplying means for multiplying said input signalinterpolated by said interpolating means by each sequence of respectivefilter coefficients producing a result for each sequence; and delay andsummation means for delaying a respective result of said multiplyingmeans and consecutively summing and delaying said delayed respectiveresults with each remaining result of said multiplying means, therebyup-converting said input signal data rate f_(s1) of said input signal tosaid output data rate f_(sh).
 2. The rate converter of claim 1, whereinsaid coefficient generating means comprise M coefficient generators forgenerating each of said M sequences.
 3. The rate converter of claim 1,wherein said multiplying means comprise M multipliers for multiplyingsaid input signal interpolated in said interpolating means by said Msequences generated in said M coefficient generators.
 4. The rateconverter of claim 3, wherein said delay and summation means comprise apipeline of alternating delay elements and summation elements.
 5. Therate converter of claim 1, wherein M equals N+1 and an N:N+1up-conversion is performed, said coefficient generating means generatesN+1 sequences of respective filter coefficients.
 6. The rate converterof claim 5, wherein said N:M conversion ratio is 3:4, said coefficientgenerating means generates 4 sequences of respective filtercoefficients.
 7. The rate converter of claim 6, wherein said coefficientgenerating means generates said 4 sequences of filter coefficients kincluding a first sequence of k11, k10, k9, 0, a second sequence of k8,k7, k6, 0, a third sequence of k5, k4, k3, 0, and a fourth sequence ofk2, k1, k0, 0.